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    Building a resource efficient CPU, the ZipCPU!

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  1. @HomaGOD, Let's see ... when I built with the keypad, I used the COLumns as FPGA outputs, and the ROWs and FPGA inputs. Here's how I went about reading it: First, output zeros on all of the COLumns. This is the normal state of the keypad. You'll sit here until something happens. If any of the ROWs, treated as inputs, produce a value other than VCC, then a button has been pressed. You can then output VCC on two of the COLumns. If the ROW inputs don't change, then these two columns were not responsible for the button--repeat with the other two outputs Once you've
  2. @tnkumar, I think if I were going to learn AXI, (once I'd gotten past the reference guides), I'd start with learning about skidbuffers. I know of no other way to meet AXI's requirements, and maintain 100% throughput, than to use some skidbuffers. (Often times you can cheat, and skip the skidbuffer, but the result--while it might work--isn't AXI compliant.) Once you know what a skidbuffer is and how to use it, I'd then move on to AXI lite. Here's my favorite, documented, AXI-lite example. I use it for everything as my starting point. (Don't use Xilinx's example design--it's broke
  3. I suppose you could use the GPIO outputs, but the more general solution would be to build an AXI-lite peripheral. Don't use the Vivado generated AXI-lite example. It's broken. You can have Vivado build the example for you, but if you do that then rip the guts out of it. Replace it with something looking like this, and then you'll have a nicely working AXI-lite peripheral that you can do a lot of things with. Once you have the basic AXI-lite slave up and running, you'll want to modify it with something like: // Write to one of two registers always @(posedge S_AXI_ACLK) if (axi
  4. The oversizing seems not to be a choice by Digilent per se, but rather the minimum standard size of a flash device. I'm not complaining. That flash was a life saver for my purposes. Dan
  5. ISE will use the beginning of your flash for your bit file. Once the bit file has been copied to the flash, the rest of the flash is yours to do with as you please. Well, to be a touch more precise, it will use the beginning of your flash for your bin file--a bin file is a bit file minus a small (36byte?) header, so they're almost the same thing. The flash size on the S6 is 16MB, and of the two bit files I have lying around, one is 334kB and the other is 273kB. You should therefore have plenty of room left over. I'd be tempted to grab the last 15MB, but you could probably even grab anothe
  6. HDMI tends to require more pins than a typical PMod can support. That said, have you looked at this PMod? It's not Digilent, but it does look like it might have some promise. Dan
  7. @mdarmanu, How "'real time" do you want your measurement to be? If you measure clock cycles on a 100MHz clock, the result time 10ns should equal wall time. In m estimation, the clocks Digilent uses tend to be accurate to within about 1-20ppm or so. If this isn't "good enough" for you, you'll need to start with a better oscillator. The GPS PMod can help, but ... it's not perfect. It will only produce a pulse to lock on to once per second. For some problems, running the algorithm many thousands of times over and then measuring seconds in this manner may be good enough--but it is a
  8. @zygot, One of the things you may be missing about that thread is that the OP is a senior engineer at Xilinx. Perhaps that might adjust your sense of how you read it. Personally, I view the conversation as a very valuable one, and I'm glad to see it taking place. Dan
  9. @kinshuks, Out of curiosity, when you say it "gets stuck" ... how long are you waiting? 200us? Shorter? Longer? Dan
  10. @Stone, The SDSPI controller is supported by the FATFS library. The necessary glue functions can be found in the software directory. The f_mount, f_open, and f_read functions are part of the FATFS library, so yes, they are supported. Dan
  11. @sneha, The project is still there, I just merged the autoarty branch into the mainline. You can find my example project here. Dan
  12. @zygot, You and I are reading this question very differently. It started out as, can I get a design that uses DDR3 without microblaze. I think that question has already been answered. The new question is how to get a design containing a MIG based DDR3 controller to operate in a test bench. That's really a separate question. Dan
  13. @lukum, I'm going to agree with @zygot here, "This is a 5 year old thread." It would make more sense to start new questions in a new thread. The statement you are asking about above follows directly from the DDR3 specification from JEDEC. Feel free to look it up if you have more questions. Dan
  14. The voltage for a given bank will always be constant, and controlled by the power provided for that bank. This is usually hardwired on most circuit boards to 3.3 Volts. Adjusting the IO standard by itself is not sufficient. Dan
  15. @chaitusvk, If you look through my rules for beginners, one of them is that you should *only* transition on the positive edge of your clock--nothing else. Most people don't quite think through the subtle clock implications of transitioning on other than a clock. If your non-clock transition happens too close to a clock edge, you could easily end up with a physical instability. The other half of that problem is that most tools, Vivado among them, can't handle the subtle timing requirements either. Try rebuilding that block so that it's on the @(posedge clk) and nothing more. See w