D@n

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D@n last won the day on January 18

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About D@n

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    Building a resource efficient CPU, the ZipCPU!
  1. how to build satellite for radio communication?

    @Riteshkakkar, That's a much longer topic, and well beyond the bounds of this forum. While you may find some folks here who have worked on satellites built for radio communication, the full topic of how to do so is ... typically beyond the ability of any one individual. You should also know that the space environment isn't very friendly to computer chips. Unlike the earth where items can be electrically connected to ground, satellites in space have no solid ground. The space environment is known for accumulating charged particles on satellites until they experience "lightning" from one side of the satellite to the other. It's also known for tiny particles of radioactive energy that can enter into a circuit and toggle bits within an algorithm. Building chips and algorithms to operate successfully in this environment is a study in and of itself. Most chips, FPGAs included, can't handle this environment. It usually takes several years of working with a particular chip design before that design can be "space qualified". In the process, the chip becomes quite out of date. As a result, the electrical technology launched into space tends to lack what is on the earth by several years. Dan
  2. can we build wifi in fpga?

    Yes. I'm not sure where'd you'd get a board that was able to support the FPGA that would do so, but yes it is possible to do so with an FPGA. Dan
  3. what is this xilinx?

    Feel free to browse the range of projects and examples discussed at zipcpu.com. These range from building a simple LED blinking project, to a serial port, a project demonstrating the external control of an FPGA, to demonstrating a full CPU that can play 4x4x4 tic tac toe. Dan
  4. what is this xilinx?

    What does an FPGA do? It evaluates logic. How does it work? It is built around an array of tables, each evaluating a logic function and storing the result. See the video above. Does it run faster than a microcontroller? That depends. For some problem sets it will. For others, the microcontroller will work better. If you just want something that will run programs, then the microcontroller will probably run faster. For example, you can build a microcontroller out of an FPGA. The result will probably run slower than a commercial microcontroller. If instead you want something that evaluates logic reliably and within hard timing deadlines, then you might find the FPGA works faster. Dan
  5. what is this xilinx?

    I was always partial to this description of what an FPGA is. Xilinx is nothing more than a Vendor who provides FPGAs. The Spartan 3 you cite above is a bit out of date, though. If you are starting out, I'd recommend you start with one of their 7-series FPGA's such as the Artix 7 found on both the Basys3, CMod A7, and Arty A7 boards. Dan
  6. FPGA with really much RAM

    @Matthias92, If your goal is realtime operation, an FPGA is usually a much better choice than many microprocessors. As @elodg recommended, consider adjusting your algorithm. A levitation tracking algorithm doesn't usually need the whole video image. Consider cropping and downsampling that image to what you need. 16x16 might well be overkill for the problem, although I don't know your entire setup to be certain. If you do that, you should then be able to drop your latency tremendously while still working at the full precision of the camera. Dan
  7. @Tickstart, All good questions. I've avoided most of them by avoiding hiring so far, although I am considering putting my first development team together, and so I'm starting to wonder what questions I'd ask from the other side of the divide--if I chose to do so. To be clear, I've been offered the opportunity to work with a group of unpaid interns, and to lead them through the process of creating an ASIC digital design. This is not something I've done before, and ... I'm not (yet) sure I'm up to the challenge. So, I'm just thinking this over. If I did it, I think I'd be doing a *LOT* of teaching ... That teaching would probably start out with a course on how to use formal methods to prove that a design works, how to test a design in simulation, and much more. That said, here's what I think I might look for in a digital design engineer should I choose to put such a team together: a *proven* Verilog capability. Sorry, VHDL designers--I wouldn't be looking for VHDL in my team. I'd be intending to use open source tools (yosys), and open source ASIC support for VHDL is lacking. By *proven*, I'd be looking for someone who has implemented a non-trivial design on hardware--the more complex the better. I wouldn't look for someone who clicked here and clicked there to build a design, I'd want someone who actually has the ability to design. I wouldn't really care too much about *how* it was done, just enough to know that it *was* done. For example, did you do simulation? Which tool did you use? How did you simulate hardware components? How did you go about finding bugs within your design? What methods did you use? What clock speed did you run at, with what hardware? Did you ever struggle with failing to meet timing? How did you solve that problem? What FPGA board did you implement your design on? How much of the resources on that board did you consume? Did you ever struggle to get that design to fit? If you were able to work on your design some more, what would you want to improve? Bonus points would be if I could examine the design on github. Among other things, I want to use these questions to weed out any designers who used Verilog to write software, or who were just placing the word "Verilog" on their resume without really having any background in using it. I'd also be looking for someone who was *real*: a human with faults who is willing to acknowledge they've made a lot of mistakes that they've then learned from. The last thing I would want on any team would be someone of substandard morality, and so I'd be using this criteria to try to weed that out as well. I'm also going to be asking about any experience using Linux or git. This might include, "How would you build a linux software package from source?", or "What is a git branch, and when would you use one?" In this case, I don't care if the answer is right or wrong, but rather if the individual can answer--again proving that he or she has the ability they say they have. Icing on the cake would be someone with all of the above experience who also had experience with computer science and specifically compilers, who was comfortable working in C++, who had experience with formal methods, digital signal processing, or even just a plain mathematical background. Being able to understand how to "prove" something is important when using formal methods and its a background that comes for free from a mathematician. Finally, given that the opportunity I'd be working with is probably less than entry level, I think I'd be surprised to even get all of this. Of course ... this assumes I accept the position. Either way, these are just the thoughts I had off the top of my head. Dan
  8. echo server on uart

    Is this what you are looking for? It's a UART echo demonstration. Keys typed into the UART terminal will be echoed back. Even better, keys typed into a TCP/IP port will go into the simulator and be echoed back on a TCP/IP port. There's no *hardware* ethernet component involved however. Not sure what you mean by an echo *server* that uses UART though. Dan
  9. Delay

    Have you seen this article? It goes about describing this Verilog delay code (here). The code is really written for signal processing, not so much LED blinking. Were you to use it, you'd probably want to slow down the LED sample rate, lest you use all of your block RAM describing a sample-by-sample delay. How exactly you'd do this depends upon your signal source. One option might be a 1-bit block averager, but like I say this all depends upon your source. Dan
  10. Possible to program Arty SPI ROM without full Vivado?

    @Paul_kimelman, If you configure an Arty with the bin file from the OpenArty project, there's a zprog.sh program that can be used to load an arbitrary bitfile. You'll need to adjust the location of the bit-file, and might also want to skip the call to wbsettime at the end. Dan
  11. My first Zybo/7010 project

    Hmm ... perhaps there's a misunderstanding here. FPGA's cannot handle internal tri-state busses, but have no problems with them on the exterior pins. As for asynchronous resets, there is a time and a place for them. Xilinx's official comment on them is to avoid them if possible. They explain this with the example of an external pin that due to RF interference or other might accidentally trip the pin, but not hold the asynchronous reset line down long enough to be ... useful and reliable. As a result of this vulnerability, some of the design might reset, but not other parts. That said, I have been successful using such resets within a design when crossing clock domains--as long as the reset is asynchronously set and synchronously released. If you can guarantee the reset will be asserted long enough to be relevant across the design, then you shouldn't have a problem. I do like your quote, though: "Resets are not at all as straight-forward as one might imagine." The devil's in the details--one of the reasons why I dislike designs that remove the designer from the details ... Dan
  12. Using Pmod IP cores without processor

    @moe, I also have the Arty board and "a few pmods". You can find my design on GitHub--I call it OpenArty. The design does not use microBlaze at all, nor does it use the schematic design approach. It is done entirely in RTL, to include support for the ethernet and the DDR3 SDRAM. This may or may not work for you, however. Although the design is entirely open, it was also written entirely in Verilog (not VHDL). Further, I used a ZipCPU within the design. As a result, all of the peripherals I created were connected to a wishbone bus, allowing them to be controlled from a CPU, an external host controller, or even your own state machine if that's how you wished to do things. I've argued on line that the first approach to any CPU-based design should be first building the code to run and be commanded by an external "host" computer--such as a PC. Even if you have no CPU within your design, you might still find this approach valuable for controlling the components of the design. I wrote extensively about how to do this on my blog. You can find the links to those articles here if you would like. Dan
  13. Resolution of Spectrum Analyzer

    @JColvin, @attila, FFT resolution is nominally given by the sample rate divided by the FFT size--not quite by the number of samples but the "number of samples" is usually close enough. This metric is based upon a rectangular window (filter) which has *horrible* sidelobe performance. Better sidelobe performance can be achieved with a better filter, often at the expense resolution--examples include Hanning and Blackman windows which will widen the response of any FFT to a tone by between 5 and 9 FFT bins at only 50dB below the carrier. Better windows are available if you'd like them, Dan
  14. @zygot, I don't think the FFT is the issue at this point. I think the issue is running one clock at fs1 into one component, and another clock at fs2 into another component. The problem was then "fixed" by making both components run at fs1, but ... by making the ready line come from a clock generator with a 10% duty cycle? This was the part I was hoping you might comment on. I have no experience doing this, and it concerns me that there might be some sleeping dragons lying in this road. In Verilog this would be *very* easy to handle. I'd be running everything at the system clock rate, which would be 82MHz (for the DDR3 SDRAM) or higher and then adjusting the "valid" signals to handle the rates. Easy. Using this "simple" GUI method, the logic items that should be simple aren't nearly as apparent to me. As one engineer stated, "there's no way to take the training wheels off." As a result, the simple logic construct I just mentiond is ... beyond my experience to instruct (via the GUI), and the alternative @subasheee has chosen (a clock with a 10% duty cycle, rather than logic)... concerns me. Dan
  15. @zygot, Any suggestions on how I should respond to @subasheee here? I think @subasheee is trapped within the graphical design approach to building an FFT based processing engine, and thus struggling with the lack of expressiveness in the graphical language, and ... unaware of the metastability pitfalls that attach themselves to the approach mentioned above. Dan