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  1. The voltage for a given bank will always be constant, and controlled by the power provided for that bank. This is usually hardwired on most circuit boards to 3.3 Volts. Adjusting the IO standard by itself is not sufficient. Dan
  2. @chaitusvk, If you look through my rules for beginners, one of them is that you should *only* transition on the positive edge of your clock--nothing else. Most people don't quite think through the subtle clock implications of transitioning on other than a clock. If your non-clock transition happens too close to a clock edge, you could easily end up with a physical instability. The other half of that problem is that most tools, Vivado among them, can't handle the subtle timing requirements either. Try rebuilding that block so that it's on the @(posedge clk) and nothing more. See w
  3. @chaitusvk, I'm not sure quite what problem you are struggling with, but I do know one thing: this is not how you go about solving a problem in hardware. Sometimes I can recognize a pattern in software and know exactly where to go for a bug, but that's been rarely the case in hardware. You have a couple of basic solutions available to you here to help you dig: My first step when debugging Verilog logic is to enable default_nettype of none, and to then run Verilator -Wall on the design. This won't necessarily catch any latches. I would then formally verify any modules of you
  4. @chaitusvk, From what you've given, I'm not sure what you are describing in total. I do know this, however: if you don't define all your inputs and outputs in the XDC file, then the synthesis tool won't do what you want. Hardware synthesis tools will aggressively optimize your design. If your design creates an output that doesn't get sent to a pin, then any logic leading up to that output may be validly removed. This is usually considered a good thing, although it has been known to surprise beginners. Dan
  5. @zygot, The Cmod S6 supports the DEPP interface. I have two separate HDL interfaces that work with this interface. This may be the simplest, but I have this one as well. To my knowledge (and memory--it's been a couple years), these boards don't export a serial interface to the host at all like most of the FTDI USB/UART devices, but rather this DEPP interface which is quite different. Dan
  6. @Brian Heilig, Would an example help at all? Here's the software I used to communicate with my S6. Yes, I call DmgrOpen followed by DeppEnable. I think the biggest difference I see off the top of my head was that I used either "" for a serial number, or a much longer string returned by djtgcfg. Dan
  7. @Helmsley, I though picoBlaze was a proprietary CPU core? If so, you won't find the Verilog code for it. You might want to check out copyblaze and/or pacoblaze. They're supposed to be clones of the PicoBlaze processor. I have no idea how well, or even if, they work, but that's just what they advertise. Beware ... this is one of the faults of the Xilinx ecosystem. Many like it. However, it contains many parts/pieces/components for which the source logic is encrypted. You will struggle to take designs from the Xilinx ecosystem and use them in any other. You should be fine w
  8. @RodRico, No, I don't have any STL files posted. You can certainly use OpenSCAD to generate one, however. That was the tool I used. It's FOSS, if that helps you at all. You can find the SCAD files in the same directory as the PNG. Dan
  9. @RodRico, I 3D printed a top m'self, not the base, but perhaps you might find this a useful place to start from. You'll find some scad files there as well, should you wish to use a tool like openscad. Dan
  10. @zygot, Yes, I have read your message. I'm not sure I'm ready to respond to it, and so I have not. Let's just say I'm still mulling it over. Go for it. Perhaps the discussion that follows (if any) will help me form an opinion one way or another. Dan
  11. @asmi I'm finding about one complaint in Xilinx's forums roughly every week to two weeks. The complaint is typically from a user whose design is locking for what appear to be completely inexplicable reasons. Digging further typically reveals that they are using one of Xilinx's demo designs--either the AXI-lite or the AXI (full) one. Whether or not you run into one of these problems really depends on how you configure the interconnect. If you configure it for "area optimization", you won't be likely to see the bug. Another key criteria has to do with how the bus is driven. One
  12. @zygot, Lol. You won't find me putting money down for such a bet either. @zygot, At the risk of taking this thread far off topic, let me ask, What sort of demo would you like to see? I have an AXI performance measurement tool that needs to be tested out somewhere. It's a solution looking for a problem at this point--much like the demo you would like to see. So, again, what sort of demo would you like to see? What particular items are you interested in seeing? Things that would be relevantly useful in demonstrating? I make no promises to implementing such a demo
  13. @RodRico, AXI-lite isn't all that bad. But the full AXI? Yeah, that gets painful. Perhaps the most painful part is dealing with backpressure. This is something Xilinx's demos don't handle properly. Backpressure is what happens when BVALID && !BREADY or equivalently when RVALID && !RREADY. In either case, your design should (ultimately) lower AWREADY, WREADY, and/or ARREADY (depending on which channel has the backpressure). Stopping up the processing along the way, especially if you have a pipelined design, can be a challenge. Here are some other challenges: A
  14. @MarkSe, Just a quick question on your test bench: Should the release from reset be synchronous with a positive edge of the clock? I've seen a lot of weird behavior associated with non-blocking assignments, enough that I try to use blocking assignments for all signals that are supposed to be clock synchronous. Dan
  15. @RodRico, Welcome back! You've also missed the AXI revolution (or hostile takeover--your pick). Beware when you dive into it today that Xilinx's examples are buggy. Dan