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D@n last won the day on June 18

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About D@n

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    Building a resource efficient CPU, the ZipCPU!
  1. @sandy3129, If all your problem is that the master bus has 32 bits and the slave bus has 4 bits, then the problem has nothing to do with AXI lite vs full AXI, and it is easily solved. Just throw away the other bits. The slave only needs to have enough bits to process the logic within the slave. AXI Full has much more capability than just having 32-bits of an interface. As I recall from the top of my head (I'd need to pull up the spec to be certain) the AXI full interface requires that slaves understand requests to read and write blocks of data, with incrementing or non-incrementing addresses and more, whereas an AXI lite peripheral only needs to be able to handle one transaction at a time. Because of the complexity of the full AXI protocol, I would recommend you stick with AXI lite as long as you can. Most home-made peripherals, to include the ones I've built, don't need the full AXI protocol. Oh, and the number of address lines is not the difference between the two protocols. If the slave only has 2^N addresses within it (each a bus in width), then it should only need N address lines and the others don't need to be connected. Just be aware of which line is the "lowest" one--there's a trick or two there. Dan
  2. @riche, With a little googling, I found this solution to your issue: Report IP status, then Upgrade all of your IP Dan
  3. @electronicsdevices, If your network autonegotiation fails, check your network cable and your router. What it means is that your ethernet PHY is trying to contact your router to determine the speed of the network, and it's not getting a response from the router. Dan
  4. Hi @nixiebunny! Welcome to the forum. I'm not sure where you are getting the top.vhd from. I do all my S6 programming in Verilog. As for starting up in a known state, Xilinx allows you to specify the initial value of any register variables. In Verilog, this looks like "initial register_name = 0;" ... or whatever value you'd like to set it to. This also works for any registers controlling output values. Further, as part of the startup sequence, Xilinx chips hold all of their output pins in a high impedence state (neither 1 nor 0) until the configuration completes. At that time, any initial values have been set and initial output values can be sent. You can also either of the buttons (or a GPIO for that matter) to reset relevant portions of your design if you would like. I used one of the buttons to reset the CPU I placed into my design if it ever got ... stuck. Dan
  5. @riche, I didn't see the 50MHz clock reference, but the data sheet for the A/D on the PMod AD1 says that the maximum SCLK rate is 20MHz. Incidentally, the PMod AD1 uses the same A/D as the PMod MIC3. As I understand the limitations of the canned demo, you might find it easier to modify a piece of regular open source Verilog, written for the MIC3, than to use the canned demo to get both samples out, synchronously. The open source solution has an optional integrated FIFO, of a parameterizable length, as well. Oh, and it's also got an open source simulation model (sine wave input) that you can use to test/prove that your interface works. Just a thought. Dan
  6. @zygot, You beat me to the punch! I've been slowly building a UART interface on my blog at zipcpu.com, and posting the code on github online. I'm just now writing up the description of the build interface so that users can run it and try it in simulation--should have that posted in a couple of days, even though the Makefiles are already in the repo. I've still got a couple of lessons to go to describe how to place transmit and receive FIFO's into the interface, to forward the interface over a TCP/IP port, and to create a software library which can then be used to request information from various "addresses" within the design. Indeed, I've been somewhat "surprised" at the number of lessons required to describe how to get an interface like the one I've designed up and running. Key features I'm including are 1) the ability to fully simulate the design using open source tools with no FPGA required, 2) the ability to forward the debugging interface across a network, and 3) the ability to get information from a scope contained within the interface. Oh, and one more ... I'm using Verilog. I expect I'll fully post my work in another week or so at the rate I'm going, as long as the trip to Grandma's house this summer doesn't get in the way. Dan
  7. @mihai5, What you *want* to do is to write to a peripheral that you can just *DUMP* data to as fast as the CPU can write it, while having the PL process it. The processing you'll want to do is going to look like a giant state machine. Indeed, such statemachines often end up so large they need SDRAM memory access. For example, to compare two strings, you'll want the CPU to dump one string to the PL, and you'll want the PL to already know the second string--perhaps from SDRAM, perhaps from block RAM. One difficult part you may not have thought about is ... what happens if you are trying to match to a string like: "HHELLO HH". How will you synchronize your pattern matcher to the beginning of this string? When you receive an H, is that the beginning of the pattern, or just the middle of the pattern? Again, after you receive "HH", what state do you want to be in? Suppose you receive the string "HHELLO HHELLO HHELLO" ... how many patterns do you wish to declare matches to? The pattern exists within there twice, but the two patterns overlap. If you can read data from the CPU, that's the first part. You should be able to do just about all of the rest in your PL. Dan
  8. @mbvalentin, Pardon me for asking, but .... why is this marked [URGENT]? I have no reason to believe that anything [URGENT] will ever be treated any differently from any other request. I don't personally own a PMod IA. That said ... This looks like one of those (common) cases that violates the fundamental assumption in all debugging: that there's only one bug. I'll start with the first one I see, though ... Looking at your first chart suggests you have a data interpretation error. As proof, consider the exceptionally large value within it. Anything that comes close to this value hits the value. Likewise there's a not quite so large value (2^23 perhaps?) and anything near it hits the value. The second chart likewise. It's as though once the impedence gets large enough, the noise gets out of bounds of either your software, the PMod, or both. Please double check how you are dealing with the sign bit within your own work. Be aware that the ARM and the PC have different default signedness for their variables. (ARM char is unsigned as I recall, PC char is signed.) Judging by the value, I would wager that a 3-byte (24-bit) value is not properly being composed. I'm also going to wager that a 20k Ohm or lower resistor wouldn't have the problem you are illustrating--not that the problem would be fixed, but rather that you would no longer see it. Dan
  9. @Rlohan, You might wish to take a look at how xilinx structures its block RAM. The hardware can only support some interfaces, not all. Multiple writes at the same time is one of those interfaces the hardware doesn't support. If you structure your block RAM resources well, though, you might manage to be creative and build multiple block RAMs that can all be written at the same time, but still act as a single block RAM unit within your design. How you do this, though, would be dependent upon what you are trying to do so ... without more information (why you wish to write to many at once, what your timing constraints are, etc.), I'm not sure what more I might suggest. Dan
  10. Have you checked the data sheet for the FT2232H? Do be aware ... reprogramming the FT2232H is not a capability Digilent really supports. Indeed, requests for "fixing" the FT2232H interface after someone has tried to upgrade it are ... rather common requests on DIgilent's site. In other words, make sure you know what you are getting into before you dive into reprogramming your FT2232H. Dan
  11. @Robert Finch, My guess is that the port isn't properly configured once it enters into your design. Are you using an IBUFDS? Dan
  12. @mihai5, I'll just say that wouldn't be my approach to the problem. If the data stream has to go through the CPU, you've already lost most of the benefit of the PL. As for being a 1-month project, be careful what you are getting into. The project could easily be a two year project depending upon your goals. If it's going to be 1-month only, make sure you start in an office that has all the tools in place and that is already successfully doing development on the board. Otherwise those nit-picking little items will kill your project, Dan
  13. @OCI, So, if you are interested in the PMod BTN, you can find the schematic for it here. You'll see there that there are many capacitors as part of that design. Dan
  14. @OCI, Are you looking for something like this? Dan
  15. @OCI, You mean this pmod? I think you can see that all the keys have not only caps on them, but also that they have stickers on them indicating which key they represent. Or, are you referencing the details of the design which can be found on the schematic, which shows no capacitors on the part? Dan