Todd Cooper

Hello Release v2018.2-1 I have a LCD with 1440 x 1440 resolution How do you set these variables in top.vhd in "Sync Generation Constants" Section for this LCD: H_FP, V_PW, H_MAX, V_FP, V_PW, V_MAX Also what pxl_clk can I use? Max? Thanks Todd Cooper

Hi JColvin, Yes, all of the PL IO pin bank voltages appear to be set to 3.3V and it looks like the Zynq 7010 disables the LVDS outputs if the IO pin bank voltage is >2.85V please see attachment. From the Cora Z7 schematic, the supply voltage for the LVDS IO pin banks 34 and 35 come from the Buck 3 Output of IC15 which is a Dialog DA9062 PMIC. This PMIC's output voltage is programmable and it's programming ports can be accessed from unpopulated connector J14. Buck 3 output is programmed initially to be 3.3V. Is it possible to re-program the DA9062 Buck 3 output to 2.5V to enable LVDS drivers on the Zynq 7010? If so, please let me know how to do this. Thanks

Hello, I can't find the micro USB connector or micro USB controller IC (IC6) on the Cora Z7 schematic. Can you please point me to an updated schematic which has these devices? Thanks

Hello, I have a Cora Z7 10 board and would like to view the routing of some of the signals on the inner layers of the PCB to determine if they can be used for LVDS. Can you please supply the PCB layout Gerber files or equivalent? Thanks