QI109

I did in fact use the test bench to ensure that both my tristate buffer and the main block that produces the communication pulses work as expected. I also tested the tristate buffers and the communication pulses individually without the PHY involved. I am well aware of the the importance of validation, it is just that I did not add it to the post as it should be presumed that that is already completed. I also ensure that I am following the voltage standards correctly which is the LVCMOS15, you can see that in the constraint files. I'd like to use the PHY MDI interface to have some customization on the Ethernet interface on the Genesys2 and create some custom cores with higher level stacks like UDP, TCP/IP without using ready-made IP cores.

There is a PHY (Realtek RTL8211E) on the Genesys 2 FPGA board that is between the Ethernet RJ45 copper pins and the FPGA i/o pins. I am trying to read a register from the PHY using the MDC/MDIO pins, but I could not get it working. This is a timing diagram from the Realtek RTL8211 documentation (Page 20): I created a Vivado project and programmed it on the Genesys2. I also added two additional PMOD pins and probe them with a scope to confirm that this is indeed what was sent to the MDC and MDIO pins. As we can see, after the frame has been sent, the PHY does not respond, that pin is still in a high impedance state, so that the PHY could communicate back with the MDIO pin. See the attached source and constraint file for more details on how the FPGA is programmed along with how I have configured the Tri-State buffer for interfacing with the MDIO pin. Any ideas on why the PHY is not responding to read requests? genesys2.xdc serializer.v

I am trying to follow the microblaze server tutorial with the Genesys2, the project straight up does not run. Supposedly it is caused by the Vivado version issue but I have already transferred my Vivado license several times and can no longer download an older version of Vivado and re-transfer the license. Can someone fix this issue for Vivado 2020?

On the Genesys 2 FPGA board, we can program the FPGA using a microsd card by putting the bitstream onto the card, switching the jumper to SD, then pressing on the PROG button on the board. However, if my FPGA design includes a Microblaze design, there does not seem to be a way to program the memory of the Microblaze CPU using the SD card. All I can do is again, add a bistream onto the card which only programs the FPGA fabric. The Microblaze itself is not programmed. If I want to also program the Microblaze CPU from the SD card, is there a way to do so?

The Genesys Zu board comes with DDR4 RAM which I have tried to use integrate with DMA but without any luck. My end goal is to send binary data from the PL fabric into the DDR4 RAM independent of the APU. May someone provide me with a list of things that need to be changed for the AXI DMA IP Core and the Zynq UltraScale+ MPSoC in order to accomplish this? I especially need instructions on how to configure the SoC for DMA because there is clear documentation on the AXI DMA IP Core but not the SoC for DMA purposes. I have already set up the AXI DMA register space correctly, but I do not know the SoC's AXI ports well. They only show up on Vivado Re-customize IP as highly abstracted out ports. I am guessing the main issue is not having the right high performance AXI interfaces enabled on the SoC. Edit 1: I came back to clarify that I am running bare metal C programs, if it matters.

I know that Genesys Zu is preloaded with linux, I would like to use it as a blank FPGA and program it with Vivado, any ideas on how to do that?