patrick poirier

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patrick poirier last won the day on December 14 2015

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  1. patrick poirier

    ARTY running MicroBlaze on FreeRTOS

    Hello Sam, OK the FreeRtos works on the Arty MicroBlaze... You can consider this post closed :-) So now I can build a processor from scratch and tailor it to my requirement, it just take a couple of hundred hours of coding, so it is not as easy and fast as uploading a blink code into a 3$ Arduino, but it does what's advertised. Thanks
  2. patrick poirier

    ARTY running MicroBlaze on FreeRTOS

    BTW, Now that I have a functionnal MicroBlaze, I will give a try to this implementation of FreeRtos : http://www.wiki.xilinx.com/file/detail/Artix7_35T.zip
  3. patrick poirier

    ARTY running MicroBlaze on FreeRTOS

    Well Sam, we are making progress !!! The new implementation for Microblaze seem to be working fine. So following the step on this wiki https://reference.digilentinc.com/arty:basedesign I builded a functionnal bin file. Looking T the IP design (see attached) , all the IO are connected. I just had time to test echo server with ethernet port and it is OK. Might proceed to additionnal test later. Now, what about implementing FreeRTOS on this baby ? Thanks for your support
  4. patrick poirier

    ARTY running MicroBlaze on FreeRTOS

    OMG.... Is this Xilinx Coprorate Stuff ? I downloaded the Zip file and it is pretty much like the echo server nomenclature , just an Ethernet implementation (No Serial , No ADC...). It is pre 2015.2 so it crashes when updating... a waste of time... Thanks for the follow-up Sam, but until Mister Burnham delivers what he sowed on the video , on the wiki pages with the same details and quality (not the punk patchwork that you found) I'll be a little skeptical.... By the way, I suggest that you remove this, from thttps://reference.digilentinc.com/arty:basedesign, === An updated board file will be available after the holiday.
  5. patrick poirier

    ARTY running MicroBlaze on FreeRTOS

    Hello, Do you have any update on this issue ? My expectation were simple: A) Get a step by step walk-through of creating afully functionnal Microblaze system with cores that communicate with all of the peripherals on the Arty using the Vivado IP. B ) Fully functionnal RTOS image including the drivers so I can really experiment with the power and flexibility of the Artix 7. Is is what I was supposed to have , or I get lost in translation looking at Jim Burnham 's video ?
  6. patrick poirier

    ARTY running MicroBlaze on FreeRTOS

    Hello Bianca, Hope that you will issue this release soon, because as you know , this is basically what this product is designed for : A MicroBlaze development platform. Please keep us updated , Best Regards Patrick
  7. patrick poirier

    ARTY running MicroBlaze on FreeRTOS

    Hello, What is the status with the the FreeRTOS running on a FULL implementation of a Microblaze on ARTY ? I bought this board for this specific purpose following your presentation video : https://www.youtube.com/watch?v=NF7ryZH8lxE Regards
  8. patrick poirier

    ARTY DDR3 Microblaze Project

    Hello, I stumbled on the same error as well. I am using Vivado 2015.4 on Windows 10 There is a step missing between 4.8 & 5.0, so I will call it step 4.9: -Double click on Concat (microblaze_0_xlconcat) and make it a single port device - Connect AXI Uartlite Interrupt line to Concat IN Then at step 6 Validate Design should end up with success And then , you are 40 minutes away to get an Hello... :-) I have not tested the echo server yet, I'll get an update.
  9. patrick poirier

    Arty_bsd problem in implementation

    Hello I just received my ARTY and try arty_bsd with vivado 2015.4 Vivado start with an upgrade from 2015.2 to 2015.4 and ends up with this: Vivado Commandsupgrade_ip [get_ips {system_microblaze_0....[IP_Flow 19-3298] Detected external port differences while upgrading IP 'system_axi_gpio_led_0'. These changes may impact your design.[BD 41-1165] The interface pin 'GPIO2' with bus definition 'xilinx.com:interface:gpio:1.0' is not found on the upgraded version of the cell '/axi_gpio_led'. Its connection to the interface net 'axi_gpio_led_GPIO2' has been removed.blabla.....There are 34 critical warning while upgrading the IPs...... Obviously, it does impact with the rest of the process and cannot generate bitfile :-( So please add this info to the ticket Best Regards