Mario875

Perfect, thanks! ?

In terms of going for the SoC board, that depends if you will have a use for a dedicated ARM hard core processor. Will you have applications that will make use of it or are you solely focused on FPGA development?
If you only care about FPGA development and want to go between the Basys 3 or Nexus A7 along side that book I recommended, honestly, as the saying goes "buy cheap, buy twice". The Basys 3 is a fantastic board, but the Nexus A7 can do everything the Basys 3 can do and more. The Nexus A7 has RAM and an Ethernet Port that the Basys 3 does not and that is where the book calls up the use of the Arty A7. However the Nexus A7 also has the 7-segment displays that the Basys 3 has that the Arty A7 does not.
So if you decide to get that book and read it cover to cover, then the Nexus A7 should be a "1-stop shop" board that you can use throughout the entire thing. However it is worth noting that the Arty A7 board is only really required for later chapter, the Basys 3 can do everything needed for most of it.
When following the book you just have to be aware that if you are using the Nexus A7 the constraint files and setting up of the board in Vivado will be different, but as long as you are somewhat familiar / savvy with these already from your previous experience of FPGA's that should not be an issue.

Hi @Mario875
Yes. The pattern generator and logic analyzer can run independently or in parallel in the device.

This book is a great start. It begins with what logic gates are and builds upon that. From a basic LED being turned on and off with a switch all the way to implementing a soft core CPU on an FPGA and beyond.
The book is to be used along side the Basys 3 or Arty A7 dev boards, but honestly, I would opt for the Basys 3 for this book as most of the early chapters are geared towards that board more so than the Arty A7.
Everything taught in here is transferable to all other FPGA's. The book covers both Verilog and VHDL simultaneously, but I would only chose to learn 1 language first and skip everything related to the 2nd language for now, you can always go back and learn it later. It is however slightly geared more towards Verilog than VHDL, but all examples and exercises are shown in both languages.
https://www.amazon.co.uk/Digital-System-Design-FPGA-Implementation/dp/1259837904

Glad it's now sorted, looks like I was correct in my last post where I said...
 
It is an issue if it's not on the board all together ?

Have you tried programming directly using the JTAG interface on jumper J17? If you have that option it would be my next port of call to rule out the USB - JTAG interface.
 
Looks like xsct can see the board, but with errors on the JTAG boundary scan. Take a look at some of these threads....
 
https://forums.xilinx.com/t5/Embedded-Development-Tools/Problem-of-Boundary-Scan-Chain-of-Devices/td-p/168196
 
https://forums.xilinx.com/t5/Embedded-Development-Tools/JTAG-chain-error-in-SDK-9-Whole-scan-chain-DR-shift-through-all/td-p/819407
 
https://forums.xilinx.com/t5/ACAP-and-SoC-Boot-and/JTAG-chain-error-in-XSCT-1-Whole-scan-chain-DR-shift-output-all/td-p/1038266
 
Looks like you need to verify the JTAG TMS, TCK, TDI & TDO lines are all in the the correct states and being pulled up properly with the proper voltages, etc. The issue could also be the NC7SZ66P5X which is a bus switch that the TDI & TDO lines go do, presumably to allow interface either via the FMC connector or via normal JTAG header.
 
However, just incase it is something this simple, you have double checked all the jumpers on the board are in the correct position, yes? Not set for say direct JTAG interface programming when you are trying to program over the USB or anything?
 
If the jumpers are all correct then it's time to sit down with the board, schematic and an oscilloscope / test gear to find the fault (which could still be under the FPGA on the BGA connections).
 
Schematic can be found here... https://reference.digilentinc.com/_media/reference/programmable-logic/nexys-video/nexys_video_sch.pdf

Thanks for all the info, seems that if I want proper timings at 1080p, 60Hz, 24-bit colour I am best just using the ADV7513 (or similar). Considering the IC's are only £14 from RS Components and they are purpose built for the job, it seems going that route is first of all, less headache and second of all, likely to yield superior results. Not to mention the cost saving vs a Genesys 2! Just need to make up a custom PCB so it can interface to the FPGA via the FMC connector, not a big deal.
 
As for the Geneys 2, I cannot justify an extra £600 over the Nexys Video, it's just not worth it, even future projects I have involving FPGA's are likely to require lesser devices than the Nexys Video, probably stuff I can do with my current Basys 3. Maybe in future I can re-visit the Genesys, but not just now.
 
However I might re-visit this topic after I get everything fully functional with my project and have completed boards made up and the project is all but finished. Just to see how well I can make it run without the ADV7513 for my own curiosity.
 
Seems that the Nexys Video should be able to do 720p & 1080i at 60Hz with 24-bit colour without too much hassle, even 1080p 30Hz with 24-bit colour depth should be fine, but getting it up to 1080p, 60Hz & 24-bit colour I think will have her running a bit hot.
 
Thanks for all the info so far, especially that IP core! Really good to have that, but I think the answer as to "how did Digilent do it on their demo" (for anyone who finds this thread in the future) is that if they are indeed outputting 24-bit colour, then the only solution has to be running the FPGA out of spec and effectively over-clock it.

Download "vivado-library" and the constraints repo. Nexys video has its own ip to get hdmi output based on oserdese2, its source code is available in the IP itself. It's called "rgb to DVI". It's enough to get 1080p withut problems. You have to put a clock wizard with pixel and serial clocks to make it flexible for any hdmi or DVI mode. I Have a "bare bones" design to get video from hdmi with that. I will upload it to my repo soon