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arya

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  1. arya
    @Yannick @D@n What I have done is took 2 dds and multiplied the outputs and fed it to fir compiler. The block design done is as in the figure. Then I created a hdl wrapper and tried simulating it..but its showing error as "design ()not found while processing module instance()" . Could you pease help me through this.
  2. arya
    How to fix this??
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