epsilon

Members
  • Content Count

    7
  • Joined

  • Last visited

Everything posted by epsilon

  1. I got this level shifter: https://joy-it.net/en/products/COM-KY051VT I'm happy to report that all four of my PS/2 peripherals are working fine when using this level shifter (without it, I only have one keyboard that works). The PS/2 PMOD would have been a better PMOD if such a level shifter was part of the PMOD, IMO. Cheers, Ruben.
  2. Thank you JColvin, In the meantime I was able to score another PS/2 keyboard at a garage sale and this one is working fine at 3.3V. I also got a PS/2 mouse, which sadly does not work at 3.3V, but I confirmed it does work at 5V (on a breadboard with a 5V supply and a scope to monitor the signals). I initially thought that this PMOD could be a solution: https://digilent.com/shop/pmod-lvlshft-logic-level-shifter/ Looking at bit more closely however, it doesn't look like this PMOD will work with one wire interfaces. You have to choose a direction with the jumpers. I guess I'll have
  3. Hi, I have an Arty A7, a PS/2 PMOD and an old PS/2 keyboard. At 3.3V this keyboard doesn't show any sign of life. I suspect it actually needs 5V. I see there's a jumper on the PMOD that allows you to hook up an external 5V supply. Looking at the schematic however, I don't see how this can work. There's no level shifter on the PMOD. The data and clock lines would get pulled up to 5V and damage the FPGA. Am I supposed to hook up the PS/2 PMOD to a level shifter PMOD if I want to use it at 5V? Btw, isn't PS/2 Vcc supposed to be 5V? Is the idea of this PS/2 PMOD to hook up a PS/2 periph
  4. Bummer. In that case, as already suggested by another user in this forum, would you consider releasing the PIC24 code you used on the NEXYS 3/4 boards to do the USB>PS/2 conversion? Thanks, Ruben.
  5. Hi, It's been a while, but if we keep asking maybe some day it'll actually happen đŸ˜€: Any progress on a USB HID PMOD board? Cheers, Ruben.
  6. Thank you Arthur. I am currently using blocking assignments (see my naive testbench code below). As a beginner I have yet to learn about the the subtleties of non-blocking vs. blocking assignment in the context of a testbench, but if the upshot is that it makes the level rising edge fall at a more convenient time relative to the state transition, wouldn't I be masking an issue instead of finding one with my testbench? Or am I looking at this wrong and will there in practice always be a noticeable pulse due to propagation delay through the state register? module dual_edge_detect_sim()
  7. Hi all, I'm working my way through 'FPGA Prototyping by SystemVerilog examples' book from P. P. Chu. I'm a bit confused about the Mealy machine based edge detector in section 5.3.1. I'll copy the source code below. It looks like if a rising edge occurs immediately before the rising edge of the clock, the resulting 'tick' pulse can be super short. So short in fact, that it doesn't even show up in simulation (see first two pulses in attached waveform). Isn't this a recipe for missing rising edges? This book comes highly recommended as a resource for learning FPGA programming,