epsilon

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  1. Bummer. In that case, as already suggested by another user in this forum, would you consider releasing the PIC24 code you used on the NEXYS 3/4 boards to do the USB>PS/2 conversion? Thanks, Ruben.
  2. Hi, It's been a while, but if we keep asking maybe some day it'll actually happen đŸ˜€: Any progress on a USB HID PMOD board? Cheers, Ruben.
  3. Thank you Arthur. I am currently using blocking assignments (see my naive testbench code below). As a beginner I have yet to learn about the the subtleties of non-blocking vs. blocking assignment in the context of a testbench, but if the upshot is that it makes the level rising edge fall at a more convenient time relative to the state transition, wouldn't I be masking an issue instead of finding one with my testbench? Or am I looking at this wrong and will there in practice always be a noticeable pulse due to propagation delay through the state register? module dual_edge_detect_sim()
  4. Hi all, I'm working my way through 'FPGA Prototyping by SystemVerilog examples' book from P. P. Chu. I'm a bit confused about the Mealy machine based edge detector in section 5.3.1. I'll copy the source code below. It looks like if a rising edge occurs immediately before the rising edge of the clock, the resulting 'tick' pulse can be super short. So short in fact, that it doesn't even show up in simulation (see first two pulses in attached waveform). Isn't this a recipe for missing rising edges? This book comes highly recommended as a resource for learning FPGA programming,