ahmed nasser

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  1. Hi @tom21091 Thank you for trying to help me. Actually i am thinking to use vivado instead of ISE and now you encourage me to do this. thanks again Regards, A.Nasser
  2. Also, i think the problem is not in the warnings because the same problem occurs even if there are no warnings or errors.
  3. Hi Tommy, The warnings are: HDLCompiler:89 - "D:\Ahmed\master\1111\xilinxxxx\Nexys4DDRboard\Master_traditional_chipscope\system.vhf" Line 103: <fft2048> remains a black-box since it has no binding entity. WARNING:HDLCompiler:439 - "D:\Ahmed\master\1111\xilinxxxx\Nexys4DDRboard\Master_traditional_chipscope\system.vhf" Line 189: Formal port control0 of mode inout cannot be associated with actual port control0 of mode out WARNING:HDLCompiler:439 - "D:\Ahmed\master\1111\xilinxxxx\Nexys4DDRboard\Master_traditional_chipscope\system.vhf" Line 193: Formal port control of mode inout cannot be as
  4. I am using Nexys4DDR board, xc7a100t-1csg324. While using ISE 14.5 or ISE 14.7, synthesize and implementation are done without errors. But, while generating the bitstream to configure the FPGA chip, this step is stucked (i.e., Generating bitstream is running and never stop) without any error. Maybe with the same design without any modification, this step is completed normally but the many times it is not. please someone help me with this point.