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  1. @zygot Thank you for the info. It seems like a baud rate of 921600 is already sufficiently high so I will just use this setting in my design.
  2. Updates: I deleted and re-added the QSPI IP to my design, configured the Board Interface to be Custom, disabled the STARTUP primitive, and constrained the relevant signals in the .xdc files just as above, but when I ran my MicroBlaze application I still did not see the SPI signals on the I/O pins I selected in my .xdc file. I also deleted and re-added the QSPI IP with the J7 board interface enabled and STARTUP primitive disabled, but again I was again not able to see any output on the scope when I launched my MicroBlaze application.
  3. Update: The sck_io signal is unavailable because I had the STARTUP Primitive enabled, which routed the slave clock to STARTUP_IO_cfgmclk_io. As stated in the AXI Quad SPI v3.2 LogiCORE IP Product Guide section Enable STARTUPE2 Primitive Parameter: "This primitive has a dedicated clock pin that can be used to provide the SPI clock to the slave memory" and in Table 2-2: "Free-running clock from on-chip oscillator. Nominally 50 MHz but is not characterized or specified in a data sheet."
  4. Updates: In the Board tab of the IP, you can select the Board Interface to be Custom, spi, or qspi flash. I had this selected as spi, which I think routed my SPI signals through the J7 SPI header on the Arty S7. The reason I found this was because, when I scoped the SPI header as a test to see if it was activated, I saw the signals from my I/O pins 10-13. In the Arty S7 User Guide, it states that I/O pins 10-13 are tied to the SPI header pins, so I think that I activated the SPI header accidentally, but constrained I/O pins 10-13 which meant that the SPI header was getting my signals from
  5. Hello, I am using Vivado and Vitis 2020.2 to build a MicroBlaze application for the Arty S7. My objective is to control a DAC using SPI. I have the QSPI IP configured in standard and running at 390 kHz. I created an interface port spi_port for the IP and constrained the port to match I/O pins 0, 2, 3, and 4 on the Arty. Finally, I initialized the XSpi instance, selected the first (and only) slave, and used XSpi_Transfer to MOSI a simple buffer. When I probe the pins on an oscilloscope, the issue I am seeing is there is no SPI clock on the Arty pin n
  6. Hello, I am using Vivado and Vitis 2020.2 to build a MicroBlaze application on an Arty S7 development board. At the moment, I have a 300 MHz clock routed to the UARTLite IP and have selected 921600 as my current baud rate. I've read in two Xilinx articles (https://support.xilinx.com/s/article/35903?language=en_US and https://support.xilinx.com/s/article/14760?language=en_US#:~:text=UART%20Lite%20can%20handle%20baud,rate%20will%20be%208%20MBaud) that I can set the baud rate to the AXI clock frequency divided by 16, though neither give a guide on how to do this. I'd like to set the baud rate to
  7. @zygot why would I need to add a delay between register reads? And why would disabling data caching solve this problem? Thank you.
  8. Hey @zygot, thanks for your response. I placed usleep(5), usleep(100), and usleep(1000) before each of the reads and it did not work. For the specific code below, failure means that the TempArray is not equally populated at each index. while(counter < 100){ // reg1 is an array index reg1 = Xil_In32(BASEADDR + SLV_REG21_OFFSET); // reg2 is the data at that index reg2 = Xil_In32(BASEADDR + SLV_REG18_OFFSET); // write to array TempArray[reg1] += 1; // increment counter counter += 1; } After I read the array index at REG21, I want to simply add 1 to the TempArra
  9. Hello, I am using Vivado and Vitis 2020.2 and an Arty S7-50 board. Something in the AXI register read is failing. The specific failures I've come across are: The AXI read will hang depending on which register I'm reading. Not only that, but if a register read fails, I will test it in a basic while(1) loop and will read/print it successfully. First, it's as if moving the register to a different part of the code causes the read to fail. Second, even registers that are unmapped in my custom IP are causing the application to hang, making it seem like the application will hang o
  10. Including the xil_io.h header removes the error and allows me to successfully run the application. I assumed that my custom IP header contained all the necessary operations, but I traced them and there was no mention of the read/write operations. Looking at my other applications, they all include files which somehow trace to xil_io.h.
  11. Hello, I am using Vivado and Vitis 2020.2 to implement a simple MicroBlaze program with a custom IP. The error I am encountering is, when I build my platform, the drivers\ folder and .bit and .mmi files in export\project_wrapper_name\hw\ are removed. I can visually witness them being removed from the platform just at the end of the build. Not having the drivers folder causes Vitis to return errors when I try to build my application. These errors are undefined reference for Xil_Out32() (I am writing to a register in my custom IP) and [makefile:38: application.elf] Error 1. Why does Vitis d
  12. Hey @JColvin, thanks for taking a look at this post. Your solution worked: I added the "main.c" file, built the program, programmed the FPGA, and ran the debugger and the board performed as expected. Regarding the tutorial, everything does appear in the correct order, the only step that could possibly be added is rebuilding the program (like you suggested) after adding the "main.c" file. Thanks again for your help.
  13. Hello, I am following the "Getting Started with the Vivado IP Integrator" tutorial using the Arty S7-50 with Vivado 2020.2, though when I attempt to create the hardware (.xsa) file I receive the error WARNING: [Project 1-645] Board images not set in Hardware Platform and when I attempt to debug the program in Vitis I receive the error Executables selected for download on to the following processors doesn't exist or incorrectly specified. Do you wish to ignore them and proceed? 1. microblaze_0. I have the arty-s7-50 board files in the Vivado new board files directory as per