rmccormack1
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Everything posted by rmccormack1
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I figured out thank you.
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So I have a program to use the UART on the Digilent USB104A7 board. Here is my code: #include <stdio.h> #include "platform.h" #include "xil_printf.h" #include "xil_types.h" #include "xil_assert.h" #include "xil_io.h" #include "xparameters.h" #include "xuartlite.h" #include "xintc.h" #include "xil_exception.h" int main(void) { int Status; Status = UartLiteIntrExample(UARTLITE_DEVICE_ID); if (Status != XST_SUCCESS) { xil_printf("UART Example Failed\r\n"); return XST_FAILURE; } xil_printf("Successfully ran UART Example\r\n"); return XST_SUCCESS; } I will also attach errors but it looks like I am getting multiple errors with these functions.
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So I am getting an error saying makefile:38 fifo_test_app.elf Error 1. I do not know why I am getting this error Here is my code: #include <stdio.h> #include <stdlib.h> #define LIMIT 32 int FIFO[LIMIT]; int front, rear; int i; int choice; void insert(); void delet(); void display(); int main() { printf("FIFO TEST\n\n"); front = rear = -1; do { printf("1. Insert\n2. Delete\n3. Display\n4. Exit\n\n"); xil_printf("Enter your choice:"); scanf("%d",&choice); switch(choice) { case 1: insert(); break; case 2: delet(); break; case 3: display(); break; case 4: exit(0); break; default: printf("Sorry, invalid choice!\n"); break; } } while(choice!=4); return 0; } void insert() { int element; if (rear == LIMIT - 1) xil_printf("FIFO Overflow\n"); else { if (front == - 1) front = 0; xil_printf("Enter the element to be inserted in the FIFO: "); scanf("%d", &element); rear++; FIFO[rear] = element; } } void delet() { if (front == - 1 || front > rear) { xil_printf("FIFO Underflow \n"); } else { xil_printf("The deleted element in the FIFO is: %d\n", FIFO[front]); front++; } } void display() { int i; if (front == - 1) { xil_printf("FIFO underflow\n"); } else { xil_printf("The elements of the FIFO are:\n"); for (i = front; i <= rear; i++) xil_printf("%d\n", FIFO[i]); } }
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So I have a program to use the UART on the Digilent USB104A7 board. Here is my code: #include <stdio.h> #include "platform.h" #include "xil_printf.h" #include "xil_types.h" #include "xil_assert.h" #include "xil_io.h" #include "xparameters.h" #include "xuartlite.h" #include "xintc.h" #include "xil_exception.h" int main(void) { int Status; Status = UartLiteIntrExample(UARTLITE_DEVICE_ID); if (Status != XST_SUCCESS) { xil_printf("UART Example Failed\r\n"); return XST_FAILURE; } xil_printf("Successfully ran UART Example\r\n"); return XST_SUCCESS; } I will also attach errors but it looks like I am getting multiple errors with these functions.
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Makefile:38 Error 1 in Vitis
rmccormack1 posted a question in Digilent Microcontroller Boards (Retired)
So I am getting an error saying makefile:38 fifo_test_app.elf Error 1. I do not know why I am getting this error Here is my code: #include <stdio.h> #include <stdlib.h> #define LIMIT 32 int FIFO[LIMIT]; int front, rear; int i; int choice; void insert(); void delet(); void display(); int main() { printf("FIFO TEST\n\n"); front = rear = -1; do { printf("1. Insert\n2. Delete\n3. Display\n4. Exit\n\n"); xil_printf("Enter your choice:"); scanf("%d",&choice); switch(choice) { case 1: insert(); break; case 2: delet(); break; case 3: display(); break; case 4: exit(0); break; default: printf("Sorry, invalid choice!\n"); break; } } while(choice!=4); return 0; } void insert() { int element; if (rear == LIMIT - 1) xil_printf("FIFO Overflow\n"); else { if (front == - 1) front = 0; xil_printf("Enter the element to be inserted in the FIFO: "); scanf("%d", &element); rear++; FIFO[rear] = element; } } void delet() { if (front == - 1 || front > rear) { xil_printf("FIFO Underflow \n"); } else { xil_printf("The deleted element in the FIFO is: %d\n", FIFO[front]); front++; } } void display() { int i; if (front == - 1) { xil_printf("FIFO underflow\n"); } else { xil_printf("The elements of the FIFO are:\n"); for (i = front; i <= rear; i++) xil_printf("%d\n", FIFO[i]); } } -
So I am programming my FPGA (Digilent USB104 A7 Board). I get a message saying that the processors don't exist or incorrectly specified. It then asks me if I should ignore. I have clicked proceed but my program is not running. Is their something I am doing wrong? MBFIFO.txt
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Makefile:38 Error in Vitis
rmccormack1 replied to rmccormack1's question in Digilent Microcontroller Boards (Retired)
Yes I do have a main function in my code. -
Makefile:38 Error in Vitis
rmccormack1 replied to rmccormack1's question in Digilent Microcontroller Boards (Retired)
I am using 2020.2. I am getting one other error saying undefined reference to main. -
Makefile:38 Error in Vitis
rmccormack1 posted a question in Digilent Microcontroller Boards (Retired)
When I am trying to build a program, I get the error makefile:38 fifomb_app.elf error 1. I do not know why I am getting this error when building? -
Running a Program In Vivado
rmccormack1 posted a question in Digilent Microcontroller Boards (Retired)
So I have code and block design for a FIFO. module fifo(i_clk, i_wr, i_data, o_full, o_fill, i_rd, o_data, o_empty); parameter BW=4; // Byte/data width parameter LGFLEN=3; input wire i_clk; input wire i_wr; input wire [(BW-1):0] i_data; output reg o_full; output reg [LGFLEN:0] o_fill; input wire i_rd; output reg [(BW-1):0] o_data; output reg o_empty; // True if FIFO is empty reg [(BW-1):0] fifo_mem[0:(1<<LGFLEN)-1]; reg [LGFLEN:0] wr_addr, rd_addr; reg [LGFLEN-1:0] rd_next; wire w_wr = (i_wr && !o_full); wire w_rd = (i_rd && !o_empty); initial wr_addr = 0; always @(posedge i_clk) if (w_wr) wr_addr <= wr_addr + 1'b1; always @(posedge i_clk) if (w_wr) fifo_mem[wr_addr[(LGFLEN-1):0]] <= i_data; initial rd_addr = 0; always @(posedge i_clk) if (w_rd) rd_addr <= rd_addr + 1; always @(*) o_data = fifo_mem[rd_addr[LGFLEN-1:0]]; always @(*) o_fill = wr_addr - rd_addr; always @(*) o_full = o_fill == { 1'b1, {(LGFLEN){1'b0}} }; always @(*) o_empty = (o_fill == 0); always @(*) rd_next = rd_addr[LGFLEN-1:0] + 1; wire [LGFLEN-1:0] unused; assign unused = rd_next; `ifdef FORMAL `ifdef SFIFO `define ASSUME assume `else `define ASSUME assert `endif reg f_past_valid; initial f_past_valid = 1'b0; always @(posedge i_clk) f_past_valid <= 1'b1; wire [LGFLEN:0] f_fill, f_next, f_empty; assign f_fill = wr_addr - rd_addr; assign f_empty = (wr_addr == rd_addr); assign f_next = rd_addr + 1'b1; always @(*) begin assert(f_fill <= { 1'b1, {(LGFLEN){1'b0}}}); assert(o_fill == f_fill); assert(o_full == (f_fill == {1'b1, {(LGFLEN){1'b0}}})); assert(o_empty == (f_fill == 0)); assert(rd_next == f_next[LGFLEN-1:0]); end always @(*) assert(fifo_mem[rd_addr] == o_data); (* anyconst *) reg [LGFLEN:0] f_first_addr; reg [LGFLEN:0] f_second_addr; (* anyconst *) reg [BW-1:0] f_first_data, f_second_data; always @(*) f_second_addr = f_first_addr + 1; reg f_first_addr_in_fifo, f_first_in_fifo; reg f_second_addr_in_fifo, f_second_in_fifo; reg [LGFLEN:0] f_distance_to_first, f_distance_to_second; always @(*) begin f_distance_to_first = (f_first_addr - rd_addr); f_first_addr_in_fifo = 0; if ((f_fill != 0) && (f_distance_to_first < f_fill)) f_first_addr_in_fifo = 1; else f_first_addr_in_fifo = 0; end always @(*) begin f_distance_to_second = (f_second_addr - rd_addr); if ((f_fill != 0) && (f_distance_to_second < f_fill)) f_second_addr_in_fifo = 1; else f_second_addr_in_fifo = 0; end reg [1:0] f_state; initial f_state = 2'b0; always @(posedge i_clk) case(f_state) 2'h0: if (w_wr && (wr_addr == f_first_addr) && (i_data == f_first_data)) f_state <= 2'h1; 2'h1: if (w_rd && rd_addr == f_first_addr) f_state <= 2'h0; else if (w_wr) f_state <= (i_data == f_second_data) ? 3'h2 : 2'h0; 2'h2: if (i_rd && rd_addr == f_first_addr) f_state <= 2'h3; 2'h3: if (i_rd) f_state <= 2'h0; endcase always @(*) if (f_state == 2'b01) begin assert(f_first_addr_in_fifo); assert(fifo_mem[f_first_addr] == f_first_data); assert(wr_addr == f_second_addr); end always @(*) if (f_state == 2'b10) begin assert(f_first_addr_in_fifo); assert(fifo_mem[f_first_addr] == f_first_data); // assert(f_second_addr_in_fifo); assert(fifo_mem[f_second_addr] == f_second_data); if (i_rd && rd_addr == f_first_addr) assert(o_data == f_first_data); end always @(*) if (f_state == 2'b11) begin assert(f_second_addr_in_fifo); assert(fifo_mem[f_second_addr] == f_second_data); assert(o_data == f_second_data); end reg f_was_full; initial f_was_full = 0; always @(posedge i_clk) if (o_full) f_was_full <= 1; always @(posedge i_clk) cover($fell(f_empty)); always @(posedge i_clk) cover($fell(o_empty)); always @(posedge i_clk) cover(f_was_full && f_empty); always @(posedge i_clk) cover($past(o_full,2)&&(!$past(o_full))&&(o_full)); always @(posedge i_clk) if (f_past_valid) cover($past(o_empty,2)&&(!$past(o_empty))&& o_empty); `endif endmodule Here is my testbench: `timescale 1ns / 1ps module FIFO; reg i_clk; reg [3:0] i_data; reg i_rd; reg i_wr; wire [4:0] o_data; wire i_empty; wire o_full; FIFO uut ( .i_clk(i_clk), .i_data(i_data), .i_rd(i_rd), .i_wr(i_wr), .o_data(o_data), .i_empty(i_empty), .o_empty(o_empty) ); initial begin // Initialize Inputs i_clk = 1'b0; i_data = 32'h0; i_rd = 1'b0; i_wr = 1'b0; #20; i_wr = 1'b1; i_data = 32'h0; #20; i_data = 32'h1; #20; i_data = 32'h2; #20; i_data = 32'h3; #20; i_data = 32'h4; #20; i_wr = 1'b0; i_rd = 1'b1; end always #10 i_clk = ~i_clk; endmodule When I run simulations, I get nothing output so I am wondering where I am going wrong in my code or simualtion? -
So I am trying to program the FIFO and the UART on the Digilent USB104A7. I have the block design for the FIFO and UART. My next step is exporting it to Vitis and create the C/C++ code for it. The code should write/put data into the FIFO/UART and then display it into Tera Term. My question is that I have no idea where to start on the code. I am hoping that someone has this code already or can help me get started.
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FIFO Block Design Using Verilog
rmccormack1 posted a question in Digilent Microcontroller Boards (Retired)
So I am designing a FIFO for the Digilent USB104 A7 FPGA. I have two goals for it. First a "Hello World" type of test to demonstrate the FIFO bus outputting data to the FTDI device. Second a loopback using the FIFO where the input gets routed back to the output so whatever we send into the FTDI device comes right back out. Here is my code for the FIFO: module FIFOAXI( prog_clko, prog_rxen, RD, WR, EN, prog_txen, RST, EMPTY, FULL ); input prog_clko, RD, WR, EN, RST; output EMPTY, FULL; input prog_rxen; output reg [7:0] prog_txen; reg [2:0] Count = 0; reg [31:0] FIFO [0:7]; reg [2:0] readCounter = 0, writeCounter = 0; assign EMPTY = (Count==0)? 1'b1:1'b0; assign FULL = (Count==8)? 1'b1:1'b0; always @ (posedge prog_clko) begin if (EN==0); else begin if (RST) begin readCounter = 0; writeCounter = 0; end else if (RD ==1'b1 && Count!=0) begin prog_txen = FIFO[readCounter]; readCounter = readCounter+1; end else if (WR==1'b1 && Count<8) begin FIFO[writeCounter] = prog_rxen; writeCounter = writeCounter+1; end else; end if (writeCounter==8) writeCounter=0; else if (readCounter==8) readCounter=0; else; if (readCounter > writeCounter) begin Count=readCounter-writeCounter; end else if (writeCounter > readCounter) Count=writeCounter-readCounter; else; end endmodule I also have attached my block design. I want to use the verilog code and implement it into the block design. I have done this using the add module. My question is, do I need to add anything else for it to work or is my block design correct already? -
I am also having this problem, but it looks like I did not complete reset it. I am using the digilent usb104-a7 board
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Digilent USB104A7 FIFO Demo
rmccormack1 replied to rmccormack1's question in Digilent Microcontroller Boards (Retired)
Do you know if their is any demos that don't use the scope or AWG? -
Digilent USB104A7 FIFO Demo
rmccormack1 posted a question in Digilent Microcontroller Boards (Retired)
Is their a FIFO demo for the digilent usb104a7 board? I would like to learn how to use it for this board. -
So I have a block design that I have created. I go through the synthesis and implementation and I get no errors. When it comes time to generate bitstream, I get this error: [DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are design_1_i/clk_wiz_1/inst/clk_out2. I want to know why I am getting this error?
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Has this issue been fixed? I am running into this problem as well.
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Vivado Wrapper Error on Digilent USB104A7 Board
rmccormack1 replied to rmccormack1's question in Digilent Microcontroller Boards (Retired)
How do I export it vitis then? Don't I need a board design? -
Vivado Wrapper Error on Digilent USB104A7 Board
rmccormack1 replied to rmccormack1's question in Digilent Microcontroller Boards (Retired)
I will try this and will see if it works. Those signals you are talking about appear on the HDL wrapper. I also have to export this file to vitis so I cannot leave the design file empty. -
So I am trying to program a counter on the Digilent USB104A7 board. I want to first do it to the LEDs so I know that it is working and them move on to the ZMOD port. Here is my code that I have for the counter: module counter(input sys_clock, reset, output[3:0] led ); reg [3:0] counter_up; always @(posedge sys_clock or posedge reset) begin if(reset) counter_up <= 4'd0; else counter_up <= counter_up + 4'd1; end assign led = counter_up; endmodule Now I am having a problem with the wrapper. I am able to get through the synthesis and implication steps. I keep getting this error when I generate the bitstream with the wrapper: [DRC NSTD-1] Unspecified I/O Standard: 3 out of 7 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: diff_clock_rtl_clk_n, diff_clock_rtl_clk_p, and reset_rtl. These errors are in the wrapper and not the code itself. I do not have these ports in my file so I dont know why I am getting this error I will need to export this file later to vitis. Any help would be appreciated.