rmccormack1

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Everything posted by rmccormack1

  1. I figured out thank you.
  2. I want to write to the FIFO and I have the Digilient USB104A& Board. I am using Vitis/SDK. How would I do that exactly?
  3. So I have a program to use the UART on the Digilent USB104A7 board. Here is my code: #include <stdio.h> #include "platform.h" #include "xil_printf.h" #include "xil_types.h" #include "xil_assert.h" #include "xil_io.h" #include "xparameters.h" #include "xuartlite.h" #include "xintc.h" #include "xil_exception.h" int main(void) { int Status; Status = UartLiteIntrExample(UARTLITE_DEVICE_ID); if (Status != XST_SUCCESS) { xil_printf("UART Example Failed\r\n"); return XST_FAILURE; } xil_printf("Successfully ran UART Example\r\n"); return XST_SUCCE
  4. So I am getting an error saying makefile:38 fifo_test_app.elf Error 1. I do not know why I am getting this error Here is my code: #include <stdio.h> #include <stdlib.h> #define LIMIT 32 int FIFO[LIMIT]; int front, rear; int i; int choice; void insert(); void delet(); void display(); int main() { printf("FIFO TEST\n\n"); front = rear = -1; do { printf("1. Insert\n2. Delete\n3. Display\n4. Exit\n\n"); xil_printf("Enter your choice:"); scanf("%d",&choice); switch(choice) { case 1: insert(); break; case 2: delet(
  5. So I have a program to use the UART on the Digilent USB104A7 board. Here is my code: #include <stdio.h> #include "platform.h" #include "xil_printf.h" #include "xil_types.h" #include "xil_assert.h" #include "xil_io.h" #include "xparameters.h" #include "xuartlite.h" #include "xintc.h" #include "xil_exception.h" int main(void) { int Status; Status = UartLiteIntrExample(UARTLITE_DEVICE_ID); if (Status != XST_SUCCESS) { xil_printf("UART Example Failed\r\n"); return XST_FAILURE; } xil_printf("Successfully ran UART Example\r\n"); return XST_SUCCE
  6. So I am getting an error saying makefile:38 fifo_test_app.elf Error 1. I do not know why I am getting this error Here is my code: #include <stdio.h> #include <stdlib.h> #define LIMIT 32 int FIFO[LIMIT]; int front, rear; int i; int choice; void insert(); void delet(); void display(); int main() { printf("FIFO TEST\n\n"); front = rear = -1; do { printf("1. Insert\n2. Delete\n3. Display\n4. Exit\n\n"); xil_printf("Enter your choice:"); scanf("%d",&choice); switch(choice) { case 1: insert(); break; case 2: delet(
  7. So I am programming my FPGA (Digilent USB104 A7 Board). I get a message saying that the processors don't exist or incorrectly specified. It then asks me if I should ignore. I have clicked proceed but my program is not running. Is their something I am doing wrong? MBFIFO.txt
  8. Yes I do have a main function in my code.
  9. I am using 2020.2. I am getting one other error saying undefined reference to main.
  10. When I am trying to build a program, I get the error makefile:38 fifomb_app.elf error 1. I do not know why I am getting this error when building?
  11. So I have code and block design for a FIFO. module fifo(i_clk, i_wr, i_data, o_full, o_fill, i_rd, o_data, o_empty); parameter BW=4; // Byte/data width parameter LGFLEN=3; input wire i_clk; input wire i_wr; input wire [(BW-1):0] i_data; output reg o_full; output reg [LGFLEN:0] o_fill; input wire i_rd; output reg [(BW-1):0] o_data; output reg o_empty; // True if FIFO is empty reg [(BW-1):0] fifo_mem[0:(1<<LGFLEN)-1]; reg [LGFLEN:0] wr_addr, rd_addr; reg [LGFLEN-1:0] rd_next; wire w_wr = (i_wr && !o_full); wire w_rd = (i_rd && !o
  12. So I am trying to program the FIFO and the UART on the Digilent USB104A7. I have the block design for the FIFO and UART. My next step is exporting it to Vitis and create the C/C++ code for it. The code should write/put data into the FIFO/UART and then display it into Tera Term. My question is that I have no idea where to start on the code. I am hoping that someone has this code already or can help me get started.
  13. So I am designing a FIFO for the Digilent USB104 A7 FPGA. I have two goals for it. First a "Hello World" type of test to demonstrate the FIFO bus outputting data to the FTDI device. Second a loopback using the FIFO where the input gets routed back to the output so whatever we send into the FTDI device comes right back out. Here is my code for the FIFO: module FIFOAXI( prog_clko, prog_rxen, RD, WR, EN, prog_txen, RST, EMPTY, FULL ); input prog_clko, RD, WR, EN, RST; output EMPTY, FULL; input prog_rxen; output reg [7:0] prog_txen; reg [2:0] Count = 0; reg [31:0] FIF
  14. I am also having this problem, but it looks like I did not complete reset it. I am using the digilent usb104-a7 board
  15. So I was playing around with FT_Prog. Now when I go to vitis/vivado/adept, I get an error saying that it cannot program/find the board. Any help would be appreciated.
  16. Do you know if their is any demos that don't use the scope or AWG?
  17. Is their a FIFO demo for the digilent usb104a7 board? I would like to learn how to use it for this board.
  18. So I have a block design that I have created. I go through the synthesis and implementation and I get no errors. When it comes time to generate bitstream, I get this error: [DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are design_1_i/clk_wiz_1/inst/clk_out2. I want to know why I am getting this error?
  19. Has this issue been fixed? I am running into this problem as well.
  20. So I have the Digilent USB104 A7 board and I am wanting to program the zmod port on the board. When I open the constraint file I see their is a spot for the ZMOD (syzygy port) but their is no code in their. I was wondering how I would program the port?
  21. How do I export it vitis then? Don't I need a board design?
  22. I will try this and will see if it works. Those signals you are talking about appear on the HDL wrapper. I also have to export this file to vitis so I cannot leave the design file empty.
  23. So I am trying to program a counter on the Digilent USB104A7 board. I want to first do it to the LEDs so I know that it is working and them move on to the ZMOD port. Here is my code that I have for the counter: module counter(input sys_clock, reset, output[3:0] led ); reg [3:0] counter_up; always @(posedge sys_clock or posedge reset) begin if(reset) counter_up <= 4'd0; else counter_up <= counter_up + 4'd1; end assign led = counter_up; endmodule Now I am having a problem with the wrapper. I am able to get through the synthesis and implication step