Sheraz

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  1. Edit 1: I'm using Vivado 2018.2 on Windows 10 Home OS build 19042.1052 I made a custom IP from the files provided in example project available at https://github.com/Digilent/Pmod-I2S2 The IP works at 22.591 MHz procuring a 44.1kHz stereo input of 24-bit depth as AXI-4 stream through its master port. The same kind of signal can be used for the Transmission as well through its slave port. So I put a loop back so I'd be sure the signal is received correctly. I have used a clock converter to match it to the clock I use for the rest of the PL. It doesn't have internal
  2. @okonomiyonda I hope you are doing Fine. I want to accomplish the same as u described. I have a USB to TTL converter and I wish to hookup external interfaces from the block design to the EMIO pins on the board. Can u point me towards some helpful samples or documents. Reagrds,
  3. @jungle Can you please share how you got this working I'm stuck at the interconnection of I2S receiver with Zynq PS. I used a couple of IPs the FiFo width converter etc. but the problem is with number of bytes. I2S sends 32 bytes but the DMA controller can handle 1. Please guide me here I'm a bit stuck. Regards, @artvvbAny help is appreciated.
  4. Hi Everyone! I need help using the following pmodi2s2 module: - https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/ I want to use it to sample audio data from microphone only. So, I've added the i2s receiver IP into my block diagram (attached) and run block automation. Following is the documentation of the IP core I used: - https://www.xilinx.com/support/documentation/ip_documentation/i2s/v1_0/pg308-i2s.pdf The following is a reference manual for the above mentioned PMOD module: - https://reference.digilentinc.com/pmod/pmodi2s2/reference-manual
  5. I have UART1 enabled on MIO 48() 49(). I can't figure out where these pins are on the board. Please help me out in finding the relevant part from the documentation. Attached is the screenshot from schematic found at: - https://reference.digilentinc.com/_media/reference/programmable-logic/arty-z7/arty_z7_sch.pdf Any help is highly appreciated. Its my first post.