Hello,
I have been trying to implement a SHA256 alghorithm on my board without success so far. Right now, nothing is failing, but when i enter a letter in TeraTerm to hash, i receive random characters. The UART module works on its own and the simulations give the right results and now i am stuck. I will attach my verilog code and 2 pictures with some timing analysis in the synthesis and implementation part. My question are as follows:
1. No paths are failing, but some of them have some high logic levels and Fanout. Even though the paths are failing, do i need to worry about that? Maybe add some pipeline levels?
2.The only warning i receive is the no_input/output_delay. When i run the UART module on its own, it works without constraining these 2. So my question is as follows: Do i need them? If so, where can i read about them in more detail. I have been looking for that datasheet(i think there should be something about this topic on the datasheet ), but for some reason i cannot find it. I would be very thankful if you can give me some advice.
Thank you in advance!
PS: I am relatively new to FPGAs and Verilog, so if you find some mistakes in different parts of the code please tell me!
