hm563562

I am using Genesys-2 board and Xilinx Vitis. I wanted to store 441 floating point data values in the memory location starting from the Base address of Mig DDR, i.e., I have an array of 441 values and I ran a for loop( and also tried memcpy ) to assign the array values to the DDR memory. The program runs fine(by fine-> I mean the values are getting correctly stored in the memory locations) till 214th element. As soon as I write into the memory location : (Base address + 215*sizeof(float)) , my program stops responding. This happens for any address greater than (BaseAddress + 215*sizeof(float)). It is like I am not able to access those memory Addresses. for(int i=0;i<441;i++){ //program works fine if this loop is used for i<215 volatile float * ptr = (float *)(MIG_BASE_ADDR + (i*sizeof(float))); *ptr=arr[i];//storing array values to memory xil_printf("%x\n",*(int *)(MIG_BASE_ADDR + (i*sizeof(float))); //prints correct values upto 214 elements of the array } I checked if the size/range of MIG DDR was too low but the size/range assigned in the block Design is 1G which should be fine for storing 441 float values. Can someone please help me in this regard. Or in general, if you have a large array, what method is used to store its content in DDR?

I am using Genesys-2 board and Xilinx Vitis. I wanted to store 441 floating point data values in the memory location starting from the Base address of Mig DDR, i.e., I have an array of 441 values and I ran a for loop( and also tried memcpy ) to assign the array values to the DDR memory. The program runs fine(by fine-> I mean the values are getting correctly stored in the memory locations) till 214th element. As soon as I write into the memory location : (Base address + 215*sizeof(float)) , my program stops responding. This happens for any address greater than (BaseAddress + 215*sizeof(float)). It is like I am not able to access those memory Addresses. for(int i=0;i<441;i++){ //program works fine if this loop is used for i<215 volatile float * ptr = (float *)(MIG_BASE_ADDR + (i*sizeof(float))); *ptr=arr[i];//storing array values to memory xil_printf("%x\n",*(int *)(MIG_BASE_ADDR + (i*sizeof(float))); //prints correct values upto 214 elements of the array } I checked if the size/range of MIG DDR was too low but the size/range assigned in the block Design is 1G which should be fine for storing 441 float values. Can someone please help me in this regard.

I am currently using Basys3 board.( Using microblaze soft processor in my design ) I am looking for a way to read and write data into bram quickly. I am using a custom ip to do the computations related to the data. The outputs computed by the ip are then stored into the bram which is then again sent to the ip which processes the data in a different manner this time around and so on.This continues for a few cycles.So data transfer in an out of bram is quite an important factor affecting the peformance of my design. I went through the method of using Axi dma, i.e., 1. Connecting axi stream interfaces with the custom ip(M_AXIS_MM2S and S_AXIS_S2MM) and 2. (normal)axi interfaces with the bram(through bram controller and then block memory generator) ( using M_AXI_S2MM and M_AXI_MM2S of the dma). Part 1: If I am understanding this correctly, then although the data in and out of the custom ip is using axi stream but the data transfer in the Bram is using axi interface only which slows down the design ( here i am assuming that data transfer through axi stream is much faster than (normal) axi which will take a lot of cycles to transfer the data in and out of bram - hence slower design. So, I would like it if someone could approve or reject ( and then clarify the right answer ) this notion of mine. And if possible tell me a better approach than this for my design. Part 2 : Although I am currently using Basys 3 Board, in future I will move on to a higher end board and will be eventually using ddr memory for my design instead of bram. So is there a way I can use bram ( in my current board ) which will resemble using ddr : Sort of like a design where my bram acts as a ddr so I can check my ideas for the application as if I was actually using ddr in the higher end board right now and not have to change much when I use this design (of basys 3 board) on the higher end board.