RTalis

yes .. target tools are giving way to fresh thinking modular solutions, let alone cross platform tools , let alone Exchange tools ( FAST protocol for eg ) Full points to Xilinx for getting this far .. even tho leaving many shipwrecks behind, that's a practical outcome of development. Personally lost half million, fiddling on WIN 25 years (without time counted, just Servers , 3rd party tools that promise the earth & cards..PHI for eg Now gentoo kernel re-builds tops list of things to do. U can keep (not) Kubernetes on WIN, under the hood as a nightmare. Keep systemD .. memory abstraction.. etc Get a minimum kernel compiled, ( that in itself is an ongoing battle ) esp with PGA toolsets that interoperate with the OS. (The kernal is the OS .. going that way ) Yet Xilinx offer a practical tool set & PCIe solution for our original Q .. giving flexibility for HLS on Alveo , & migration to optimization on the Desktop !! https://www.xilinx.com/publications/solution-briefs/xilinx-algorithmic-trading-solution-brief.pdf What do u think ? pushing the flip from hard core FIN to low level tinkering .. one can still tinker with Vitis on ALVEO, thats great ! also a choice of package .. that must weigh in favor to Al-go obviously well chosen career path (Fintech) thats on fire, and cannot be deprecated in advice to lowly starter packs ( OK to get feet wet, but also a potential turnoff to a career path ) Advice : All or nothing https://www.xilinx.com/products/app-store/alveo/reference-apps.html?resultsTablePreSelect=xlnxacceleratedworkloads:Financial Computing with career path in mind , certainly time to save / borrow / parent loan into a serious platform able to tap into the market data stream, otherwise inaccessible Much better to have VITIS than more powerful 8K5 board with KU115 , based on interface to critical runtimes already developed ( the Wheel ) & supported Until u fiddle with em.. in HLS ( my Q on that.. is it even possible to modify layer 0 / 1 drivers as supplied in this kit ? ) they would be binaries or Source ?

Fun post, on opposite poles of advice .. Zygot (with his good work) a purist , XC a pragmatist .. Zygot forgets his lament on broken build tools , and how much time is spent in workarounds A miserable fact of this industry, esp in PGA , unless U buy a Data I/O ( i think obsolete) Why invite a nightmare to a newby when alternatives abound AS to hiring a programmer, XC gave better advice when costs were only mildly affected. Zynq / ARM combo. Better to buy a PCIe Dev Board for $1200 than years wrestling with protocols used in trading on unsupported EVM (& look at Exchange industry and what it offers ( like tick real time price data & volume) IF that's your business target. Why buy TEMAC IP license $1000 to $4500 for cores when functionality is built into a Dev board free. Are u going to emulate a NIC or work in AI with Exchange data ? YEs zygot will recommend coding a NIC in VHDL, FIFO s , handlers, buffers , Packet inspection , Firewall rules, threaded event loops, a full stack, then Array processing Sounds like fun. The wheel comes infinitely shaped in this age of revelation. Note u changed course from Wall St challenge to a job at the hub factory. Very educational And u may invent a new type of wheel. Tho with right inclination you may create a intuitive PGA macro library to allow smoother work in a block diagram flowchart. That would be worth an adventure providing you gained sufficient background in related art along the way. tho if u find yourself back in the original pursuit of high frequency / low latency then get the 8K5 KU115 board for $3860 from Alpha Data when u can afford tools. https://www.xilinx.com/products/boards-and-kits/1-dw5yg1.html as the best hardware or develop modular, ask Z to port this to Octave (not sure it has simulink) https://www.xilinx.com/products/design-tools/vivado/integration/addon-matlab-simulink.html .. Unless u think to create your own macro library from scratch. there u have 2 alternate industry standards. good luck with the guitar

Since before time man misrepresents product for profit. OK i like Xilinx KU115 Ultra on 8K5 board with 16GB 2bank RAM & 4 optical 40GB ports & 2 InfiniBand SFP+ ( hurrah get away from that <moderated> PCIe bottleneck) yet Xilinx still cant design a board like this Alpha Data & priced at $3800, its also IBM P8 / 9 CAPI (finally a good Arch) Now that Xilinx has a combined staff of 13,000 engineers , and i kno how they "hide behind" workloads ..may volunteer to manage a new AMD Epic that does away with software supervision outside the kernel . ANd here Xilinx were pouting about kernel byoass , where user space is handed control of runtime permissions. No wonder their Vivaldo is broken , with RDMA from 3 standards, Linux kernel now amorphous rather than monolithic , and soon to become the OS the OS always gets in the way of production ..its obsolete. BEsides monthly kernel changes break many libraries any managed suite relies upon i personally like eBPF with control plane granularity in the core , i wonder when Compilers move to a different event loop supervision model, to kill of OS dependence\ The kernel is the new OS .. yet another issue is speculative execution . it needs termination for smooth workflow, CPU is dead as well, try telling a compiler.