Elisheva

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  1. this is my code using the artix A7-35T board: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Single_bit_final_counter is Port ( LTF_signal : in STD_LOGIC; reset : in STD_LOGIC; Tgate_sel : in STD_LOGIC_VECTOR(1 downto 0); master_clock : in STD_LOGIC; MMW_source_mod : out STD_LOGIC; result : buffer integer range 0 to 10000000); end Single_bit_final_counter; architecture Behavioral of Single_bit_final_counter is component frequency_divider is Port ( M_C : in STD_LOGIC;