DelmasRanger

Like you said , The projects had to be built up from the ground up . And I also think I made a mistake in using common shared project folder instead of clearing them between try's . After all of that I got the TCP examples to work . I guess my problem is that I want to fast track my understanding so that I can get right to doing the actual project work I want to do . My next hurdle is the getting the XADC to work on DRP , looking at the various forums it seems like there is more than one way to initialize this and some boards have add-ons that make it easer to configure/interface with . Is the a example for doing very basic analog based condition handling in Verilog ? Some of the best examples i come across seems to be shared coarse work , but the problem there is that not all the source code or device configurations is available to give context to the example . I'll check the example you are referring to . Thanks again for your help and patients .

So the errors I get is : Description Resource Path Location Type make: *** [makefile:38: TCPNEW.elf] Error 1 TCPNEW C/C++ Problem Description Resource Path Location Type make: Target 'all' not remade because of errors. TCPNEW C/C++ Problem Description Resource Path Location Type undefined reference to `__bss_end__' TCPNEW line 430, external location: d:\xilinx\vitis\2020.2\gnu\aarch32\nt\gcc-arm-none-eabi\x86_64-oesdk-mingw32\usr\libexec\arm-xilinx-eabi\gcc\arm-xilinx-eabi\9.2.0\real-ld.exe: \usr\src\debug\libgloss\3.1.0-r0\newlib-3.1.0\libgloss\arm\crt0.S C/C++ Problem Description Resource Path Location Type undefined reference to `__bss_start__' TCPNEW line 430, external location: \usr\src\debug\libgloss\3.1.0-r0\newlib-3.1.0\libgloss\arm\crt0.S C/C++ Problem

Great , so its not me being completely incompetent . Because to me allot of the issues seems on the back end , like you said , somewhere in modifying and passing on info things get lost , on the front end I just see compiler errors like "cant make file .. " or error "reading link file ", which give me nothing to work with to resolve the problem . As you said ,most of my success is starting new projects from scratch . the catch is I am to lazy to code everything from the ground up and I don't want to give up now . I have had some experience with the NiRIO in a lab setting . My brain is wired like a FPGA as logic never follows a sequential approach , so I really like coding in Verilog . Any how , my reason for going down this route is that I need build a machine controller , which has all the bells and whistles for coms , telemetry and process control , whilst on the PL side have real time computational power for modulating a power source based on closed loop feedback from the ADC . So far I can only see examples of the XADC residing in SL , is there a way to access the XADC from the PL side , I do understand that on the low-level end there is more to it then just comparator channel reading , but is there a way to keep the PL-SL XADC as short as possible so that i can use the analog signals allot quicker ? I will start the TCP IP project this weekend , just tried rolling back to vivado 2018.2 to see if I can gain ground like that . Thanks for the support !

Thanks , yea, just too may errors to mention here so I'll pick a specific TCP IP example and run with that in this thread . It seems that most errors I get is when taking the 2018 example IP and code , and import it into 2020 that there is some forward compatibility issues , even when running the update wizards . Some times the project/source code files cant find headers that are in the library even when all directory's are appropriately assigned . So it would be great if someone has a TCT/IP example project they can share ,already configurated for 2020 Vivado /Vitus, deployed and tested on the Cora Z7 , and then I can intuitively work back from there . One thing I hope the community could help me find is where the USB A/B sockets are wired to as the schematics shows USB -A wired to IC-3 , but what about the USB-B host ? I assume its on sheet 6 of 11 on the Cora Z7 schematics , but those flying leads don't have corresponding terminal markers , same as with the UART leads on page 7. Thanks in advance

I'm new to the whole PL SL scene . I am working through plenty examples to tech my self how to code and get the most from this board . However no matter how much googling I do , I cant find a TCP/IP example that I know works on this board , i.e I assume the ZYNQ-7 series examples should all be compatible to a degree, yet no luck when implementing the example code . I've tried plenty , could someone who has a functioning TCP/IP project on this setup share it with me so that I can trace the cause of my issues . Like wise I cant get any USB host examples to work on my board , so any help there with a suited example would be apricated . Thanks !