cristian.ignat

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cristian.ignat last won the day on December 15 2015

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About cristian.ignat

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  1. Hi, The easiest way to implement a VGA component is to use 2 counters, one for Horizontal and one for Vertical scanning. The output signals for the VGA component should be also the HA and VA. That means that you know the current VGA address. You can find a VGA component, in VHDL, in attachment. The resolution for this component is 640x480 pixels but you can change this if you are using the correct timing. Please see link Cristian vga.vhd
  2. Hello, In order to display your pixels on the screen, you should interogate your horizontal address (HA) and vertical address (VA). If your address is the same as your wanted displayed pixel then you should send the pixel to VGA. For example, if you want to display the BRAM data between X and X + 99 for Horizontal and Y and Y + 99 for Vertical, then you should interrogate your HA and VA. If HA = X and VA = Y then you should send to VGA the BRAM data from address (0,0), if HA = X + 1 and VA = Y => BRAM address = (0,1) and so on. Cristian
  3. Hello, You can measure the current using INA219AIDR with I2C communication. You can see the connections between the INA219 and the power sources on page 21 from the schematic: https://reference.digilentinc.com/_media/genesys2:genesys2_public_sch.pdf Also you can find the SDK library in ...\demo\sdk\demo\src\INA folder from the Demo archive: https://reference.digilentinc.com/_media/genesys2:genesys2_release.zip INA219AIDR datasheet: http://www.ti.com/lit/ds/symlink/ina219.pdf Regards, Cristian
  4. Hello, Unfortunately we don't have a HDL component for LTC2481C. On Basys3 you could measure the current with a multimeter but you should modify your board and we didn't recommend this. Regards, Cristian
  5. Hello, The loading data from the microSD to FPGA can be done using a PIC24 microcontroller. The PIC24 read the first bit file and send data from that bit to the FPGA. Then a selector means to implement a PIC24 software where a selected bit file is readed and after that data is send to the FPGA. Unfortunately our project is not public but you can implement your own SPI communication with the microSD card and a slave serial communication with the FPGA to program. Please see the XAPP502 document for the slave serial communication: http://www.xilinx.com/support/documentation/application_notes/xapp502.pdf Cristian
  6. Hello, You can measure the current on Atlys using LTC248IC with I2C communication. Please see the last page from the schematic: https://reference.digilentinc.com/_media/atlys:atlys:atlys_sch.pdf You can find the datasheet for that component on the following link: http://cds.linear.com/docs/en/datasheet/2481fd.pdf Unfortunately this cannot be done on Basys3 because there are not some similar components for current measurement. Regards, Cristian
  7. Hello, I was trying and for me it works. I followed the steps: 1. Download board files from the following link: https://github.com/Digilent/vivado-boards/archive/master.zip 2. Extract the archive and navigate to the folder: C:\Users\...\Downloads\vivado-boards-master\vivado-boards-master\new\board_files 3. Open the Vivado board file folder: C:\Xilinx\Vivado\2015.4\data\boards\board_files 4. Copy from the extracted archive the "zybo" folder into Vivado "board_file" folder. 5. Restart Vivado This should work
  8. Hi melpin, In FPGA is better to use the sequential digital electronic. For example, the best practice is to use a flip flop using a synchronous reset: process(clk) begin if(clk'event and clk = '1') then if(reset = '1') then q <= '0'; else q <= y; end if; end if; end process; instead of asynchronous reset: process(clk, reset) begin if(reset = '1') then q <= '0'; elsif(clk'event and clk = '1') then q <= y; end if; end process; Each process should begin with rising / falling edge and all logic should be done in that rising edge IF. If you want to divide a clock, then you should use a construction similar with a Flip Flop with Clock Enable (CE) pin: counter_divider: process(clk) begin if(clk'event and clk = '1') then if(clk_divider = "1111_1111") then --here you should replace with your value clk_divider <= (others => '0'); clk_CE <= '1'; else clk_divider <= clk_divider + '1'; clk_CE <= '0'; end if; end if; end process; your_process: process(clk) begin if(clk'event and clk = '1') then if(clk_CE = '1') then --your logic end if; end if; end process; For example, the following code is not ok, here you should use clk rising edge first: --------------------- Outputs at each state ---------------------------------process(prsnt_s, control_word,clk)begin case prsnt_s is .............. Cristian
  9. Hello, you should check your XDC file and the connection to XADC wizard. Also you shouldn't let some XADC pins unconnected. Can you attach your project here? Cristian
  10. cristian.ignat

    zybo xadc

    Hello, If you want to use the XADC as a ADC then in Basic window select "Channel Sequencer" and in Channel Sequencer window select the "vauxp6/vauxn6", "vauxp15/vauxn15", "vauxp7/vauxn7" and/or "vauxp14/vauxn14". Please pay attention because XADC pins supports only 0V:1V or -0.5V:+0.5V deferentially. Please see the following topic: Cristian
  11. Hello, In attachment you can find the UCF file used for DDR validation. Regards, Cristian mig_7series_v1_9.ucf
  12. Hi, We recommand to install the latest version of Vivado/SDK To generate the .elf file for Zynq you have two possibilities: 1. Right click on the project -> Run As (or Debug As)-> Launch on Hardware (System Debugger) (see image 1) 2. Click on the project and after that go to menu: Run -> Run Configurations... and in Run Configurations window right click on Xilinx C/C++ application (System Debugger) and select New (see image 2) Regards, Cristian
  13. Hello, If you want to use block design then you should re-customize the IP and if you want to use the VHDL file in Vivado, then you should modify the generic parameters. Regards, Cristian
  14. Hi, You can find the example on the following link: https://reference.digilentinc.com/nexys-video:hdmi To run this example, you should have vivado 2015.3. You can find the HDMI project on ".../NexysVideo-master/Project/hmdi" path. If you are following all the steps, this should run without errors. Your error is strange because in our xdc file, we don't have the TMDSn signal defined. Regards, Cristian
  15. Hello, Check the xdc file. For the buttons, you should have the following lines: set_property PACKAGE_PIN R18 [get_ports {"btn<0>" }]; #IO_L20N_T3_34 set_property IOSTANDARD | IOSTANDARD=LVCMOS33 [get_ports {"btn<0>" }] set_property PACKAGE_PIN P16 [get_ports {"btn<1>" }]; #IO_L24N_T3_34 set_property IOSTANDARD | IOSTANDARD=LVCMOS33 [get_ports {"btn<1>" }] set_property PACKAGE_PIN V16 [get_ports {"btn<2>" }]; #IO_L18P_T2_34 set_property IOSTANDARD | IOSTANDARD=LVCMOS33 [get_ports {"btn<2>" }] set_property PACKAGE_PIN Y16 [get_ports {"btn<3>" }]; #IO_L7P_T1_34 set_property IOSTANDARD | IOSTANDARD=LVCMOS33 [get_ports {"btn<3>" }] Also you should check (in sdk) that the button GPIO address is ok. Please attach the project if you want to help you more. Regards, Cristian