Tomas Sarquis

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  1. Hello @zygot, thank you for your reply. I got your point about "posting the code and hoping someone to fix it", but I did it because I may have some bad connections and this is one way of show you how the connections are made (maybe a diagram would be better?). The purpose of the design is quite simple: digitalize some AC signals and then process them. I didn't think about the testbench thing before now... but, ┬┐how could I simulate the IP behaviour without synthetizing and using the "real" ADC? I should simulate all the internal signals and responses? That sounds pretty comp
  2. I'm trying to get the ADC1410 to work in the Eclypse Z7 FPGA board with a verilog-pure program, making use of the IP Core provided by Digilent (ZmodADC1410_Controller_0). Up to now, I'am reading trash data from the IP output, so I suppose I've made a mistake in the connections or in the data acquisition or something else. I've not seen any example of a verilog instantiation of the IP, so please let me know if there's any out there. For making the connections, I've followed the schematic in the reference manual. I'm posting my top level design and I'm also attaching the constraint
  3. I'm having the same exact issue @Cherif, did you find any help besides @zygot's? It's not very clear for me... I'm working with the Eclypse Z7 board and I just want to use the UART/USB interface.