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B. Nasir Ashfaq

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  1. Hello, I am using ZMOD DAC with Eclypse Z-7 board, and I have two questions regarding controlling ZMOD DAC 1411 output voltage: 1) How do I switch between the low gain and high gain setting in ZMOD AWG (ZMOD DAC 1411) to shift between +/-1.25V and +/- 5V setting using the ZMOD DAC LLC IP in Vivado? 2) I want to control the output voltage levels of the DAC. How do I change the signed 14-bit values in my Verilog module to achieve the desired output voltage? The reference manual shows the following equation for controlling the 14 bit value: So for example, if I want to have voltages between 0 and 3 V, how do I set CA, CG and Range (which is again related to High/Low gain value from Q1 above) values using LLC IP in Vivado? How do I interpret Vout in this case? The LLC IP shows as follows: Please provide me with some help in this regard. Currently, I am giving between 14'd0 and 14'b01111111111111 and I am only seeing between 0-670 mV on oscilloscope with trigger setting of 50 ohm DC (and ~0-1.3 V with trigger setting of 1 M ohm DC). Please let me know if you need more information from me. Thank you, Nasir
  2. Hello Steven, I am facing the exact same problem as yours. I am working with two Genesys ZU 3EG boards and am integrating them with ZMOD DAC and ADC. We are migrating our design from Eclypse boards where both DAC and ADC LLC IPs worked fine. For Genesys ZU, the DAC LLC IP in Vivado was upgraded easily and the ZMOD DAC integration was done fine with Genesys. But at the ADC side, I faced the exact same issue as you described, and would want to know if you were able to upgrade the ZMOD ADC LLC IP for Ultrascale+ and could make it work in Vivado. As per your description, I tried manually adding the Ultrascale+ devices to compatibility device list of ZMOD ADC LLC IP, but the implementation failed with the following error: As described in (https://www.hackster.io/pablotrujillojuan/single-tone-detector-with-genesys-zu-and-rtu-728c3f#toc-developing-zmod-adc-driver-for-genesys-zu-6), I believe the error is caused due to incompatibility of IDDR primitive and the requirement to use IDDRE1 primitive instead. As a result, we are currently using the ADC driver Verilog code developed and shared in the above mentioned reference project, but our ADC sometimes works okay while other times provides glitchy and inaccurate results as observed on ILA. So I wanted to ask if you were able to find a work around for the LLC IP, or what other method did you use to make ZMOD ADC work with Genesys ZU board. Looking forward to hearing from you. Do let me know if you need any further information. Best, Nasir
  3. Hello there Zygot, I am really thankful for your investigations. We had emailed Digilent's technical support too during this time and had informed them of the problem. They have responded and have now requested us to send the board for replacement. They said that "the issues are localized around the Platform MCU, controlling the fan and the VADJ voltage as commanded by the FPGA." They asked us to report the status of PMCU LED (LD21) on boot-up. From the manual: "After Platform MCU startup, if no issues were encountered, this LED should blink in a pattern Long Blink – Short Pause - Long Blink – Long Pause then it should turn off. " But in case of our defective board, this LED doesn't turn on at all. We'll now be sending the board for replacement. Thanks again for your support. Best wishes, Nasir
  4. Hello, Can you kindly suggest how can I check for this initialization process? To enable power supply for SYZYGY, following the information from reference manual and the example projects, I am providing 1 to VADJ_LEVEL0 and VADJ_LEVEL1 and then am creating a falling edge on VADJ_AUTO (using vhdl in PL). But I believe you're asking me to check a kind of initialization process which is happening prior to that. Can you please share more details? One additional comment. These two boards were ordered from two separate places. The one with DAC/ADC issue (board B) also shows two other issues as follows: 1) the fan stops running after 10 seconds on each boot up. It doesn't run again throughout the duration that the board is switched on. 2) Getting started manual says that the programming mode select jumper is set to SD at the time of manufacturing. But when we unboxed this board, that jumper was on QSPI instead of SD, and the out-of-box Petalinux image in the SD card also didn't work when we did change the jumper to SD. We had to then take the SD card from board A and inserted it in board B for running initial tests. Thank you, Nasir
  5. Hello, We have been developing a real time data transfer application using Genesys ZU-3EG boards along with Zmod DAC/ADC pair. We previously built the application on Eclypse boards and now are migrating the design to Genesys boards. In the process, we have discovered that one of the two Genesys boards is failing to power up the DAC and ADC pods regardless of the fact that our designs are running exactly the same initialization protocols for both of them. We have verified this by inserting both the DAC and ADC pods to both Genesys boards and running some tests. On one board (board A), both DAC and ADC pods prove to be working. For DAC, this is verified by seeing DAC output on Oscilloscope when running our TX design, and for ADC, this is verified by giving an external signal to ADC and observing ILA outputs while running our RX design. On the other board (board B), ADC output appears to remain constant as seen in the ILA regardless of whichever signal we provide through the signal generator. Additionally, DAC's low-level controller IP in Vivado has an init_done_n signal which goes low after it is initialized. In the case of the working board (A), we see this signal going low, and the DAC works, but in the case of the non-working board (B), this signal remains high, meaning the DAC configuration is not done, and we don't see any signal at the DAC output. Observing this init_done_n not going low on the DAC in board B actually made us realize the problem after which we ran these additional tests for verification. All jumpers settings of both boards are the same. We are using jtag mode for programming the PL. Finally, it is to be noted that PL and PS are working okay on board B. It's just the DAC and ADC pods that are not responding. What do you believe is the problem? Are we facing a production based error on SYZYGY connector on board B? Any suggestions on how to proceed? Thanks, Nasir
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