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Varad

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    Varad reacted to zygot in Efficient way of reading EMIO pins and store the result into text file in SD card   
    So now you're using the Zedboard... Ok, so your connection scheme implies that what you are connecting to is supplying DDR data; 2 bits per clock edge = 4-bit data per clock cycle. That's an unusual format for supplying complex data samples. JA on the Zedboard is a slow standard PMOD but at least 2 pins are connected to FPGA SRCC pins, so that's in your favor. Capturing DDR data at a 30 MHz clock rate on a standard PMOD is highly doubtful. Regardless, you will have to assemble the DDR data into 4-bit data samples before sending the IQ data to storage.
    Based on the information that you've provided I believe that I've given as much help as I can. As to using AXI IP for transferring data from the PL to the PS or PS controlled external memory that's part of your task to see what IP Xilinx has to offer and choose what's preferable for your project. There are IP guides available through the Document Navigator installed with the tools.  Though there are AXI IP that can DMA data directly from the PL into the PS controlled DDR memory, trying to do that for ~30 MB of contiguous data is not for beginners. Also, most Xilinx IP comes with an example project that demonstrates at least one way to use the IP. It gets into your project when you generate the IP. If you don't have any idea what IP is available for your HW platform you can see a list in VIvado from the IP catalog while making your board design.
    Student projects get into trouble because the design process is usually out of order. First a hardware platform is chosen based on cost. Then a wild guess as to how parts of the design concept might be implemented is thrown out and everyone goes off on their own and hopes that they can figure out how to make that plan work. Then after a few experiments the problems pop up and then the panic sets in. Engineering is cruel to the under prepared...
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    Varad reacted to zygot in Efficient way of reading EMIO pins and store the result into text file in SD card   
    I think that I had understood how your HW project design was set up. What's not clear is the functionality of the signals that your exported GPIO are connected to. It's hard to make an assessment without knowing something about what the external signals are doing.
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    Varad reacted to zygot in Efficient way of reading EMIO pins and store the result into text file in SD card   
    It's not clear from your description exactly how your HW interface is supposed to work because it's not clear how the external "RF Front-end" signalling is defined.
    Connecting ZYNQ ARM GPIO to external signals and polling the states asynchronously is not, in general, a good way to capture data. A better way would be to implement an interface in HDL in your PL design and then transfer the results to the ARM cores through one of the AXI busses.
    Using the SDK GPIO drivers will not achieve the maximum possible data throughput.
     
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