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  1. @Niță Eduard Thanks for your answer, I did not use the external power supply. I try to fix this issue by restarting my laptop.
  2. Hi, everyone here. Now, I have tried with my Pmod AD1. I used the demo code provided by the Digilent, but the value shown in the Vitis Serial Terminal is different from the value I have seen in the multimeter. For example, when I insert my sensor A into the channel A0, the value shown in 2.56. The value shown in the multimeter is 2.9V. When I insert my sensor B into the channel A1, the value shown in the Vitis Serial Terminal is 1.08. The value shown in the multimeter is about 2.1V. I did not change anything in the demo code, is there anyway to allow the AD1 reading to be
  3. @efkean @JColvin Today, I tried with my Pmod AD1. However, the value shown in the Vitis Serial Terminal is lower than the value shown in my multimeter. Do I need to change the demo code in order to fix this issue?
  4. hi, I have been facing issue and I want to figure out what type of reasons can cause it? Connection issue? Or sth else? For installing my program into the zybo board, it sometimes works while sometimes pop up this error message. Like intermittently working. Here are some error message: targets -set -filter {jtag_cable_name =~ "Digilent Zybo Z7 210351AD668FA" && level==0} -index 1 fpga -file C:/Users/lukel/workspace8/test_3/_ide/bitstream/design_7_wrapper.bit targets -set -nocase -filter {name =~"APU*"} loadhw -hw C:/Users/lukel/workspace8/design_7_wrapper/export/
  5. @JColvin Thanks so much for your help. I can generate my bistream and export my xsa file into Vitis. I run my sample xadc code and it works! Now, I also can manage to upload my pH data into Thingspeak. Now, it is some small issue of inaccurate sensor result, but that is not about the fpga issue.
  6. Hi, @JColvin Thanks you for answer me the question. In actually, I have done the similar block design with the block design you have sent to me. It can successfully generated the bistream, but when I insert my xadc code into the Vitis, let my zybo board to run the program and connect my pH sensor to the zybo baord, the zybo board cannot sense the induced voltage of the sensor. (I think the reason is I never make my xadc vaux14 and vaux7 to external. when I make these two to external, my zybo board can sense the voltage). Regarding to the question you asked me, I never use the xadc file fo
  7. @JColvin Thanks for your answer. The error is implementation error. I can see that the difference between your block diagram and my block diagram is I add the external port for Vp_vn, Vaux7 and Vaux 14. And I set up 100MHz frequency for the Pmod ESP32. For set up, I connect my analog pH sensor signal pin into the the voltage regulating circuit. Then, I make a connection between the Zybo port Port A AD14 and the end side of the voltage regulating circuit. If I only insert the xadc wizard into the block diagram, the bitstream can be generated and I can receive the induced voltage of the sen
  8. I have tried to use built-in xadc to acquire the analog sensor value. Now, I want to send my data from my analog sensor and other Pmod sensors to thingspeak through using Pmod ESP32. Here I find some trouble. In block design, there is always an implementation error. However, if I drop the ESP32 away from the block design, I can generate the bitstream, export to Vitis and get all the data in Vitis serial terminal. Next, I tried to integrate only the sensor and esp32 into one block design, it failed again. I will show you the screenshot below for better illustration. I suspected the
  9. I think based on my understanding, I should draw my block diagram in this way. I connect the AQS to JC port and connect the J2 of the aqs to the J1 of the hygro.
  10. Thanks so much. Maybe I confuse with meaning of "daisy chain". But what i am worry is how to configurate this into Vivado block design, as well as the coding part when the xsa file in vivado exports to Vitis IDE. Should I use the IP core of AQS and HYGRO for block design? Or Should I use the AXI IIC only? My intern supervisor told me that for port JF i may not need IP Core. But JB to JE need IP core. I am worried that if it works only when it places on JF port because I need to use JF port for my LED and Water pump control. Sorry that I am new to FPGA and still catching up with some fund
  11. I am currently doing the vertical farming project. And I want to put my Pmod HYGRO and Pmod AQS sensor into the same port JC. I have tried to put my Pmod HYGRO and Pmod AQS into different Pmod ports successfully. Now, I just want to combine these two sensors into one port. For example, for port JC. I want the top layer of the port connect to Pmod AQS and the bottom layer of the port to the Pmod HYGRO. So what is my first step to do when comes to vivado block design and how am I going to write my Cpp code into Vitis IDE? I did some primary research on this topic before. I may n
  12. By the way, I have already tried to use two different port to connect two different Pmod sensors like few days ago.
  13. I am thinking if I can connect the specific pin in the port JC with specifc pin in the Pmod HYGRO or Pmod AQS? Maybe from PmodOut. I am not so sure?
  14. Thanks so much for your long explanation. May I ask can your one works for JC connection? I don't want to use JE. And I realise that JE and JC are different type of port. I am currently doing the vertical farming project and I want the JE to be used for relay to control the LED and water pump. Now, I may give up on IOXP and use the first layer of JC port for AQS connection and second layer of JC port for HYGRO connection.
  15. ALSO, for this part Edit: Actually from what I can see you can daisy chain the PmodHYGRO and the PmodAQS by connecting one into the other without needing additional connectors/cables since their SDA and SCL pinout match perfectly. Will it affect the block design in Vivado and Vitis as well?