Cristian.Fatu

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Everything posted by Cristian.Fatu

  1. Please take a look on this forum topic, it might help you:
  2. In order to get the needed "separate serial port on the board" you could use the Pmod USB-UART. In order to use an USB-UART device you should implement an UART communication on the corresponding pins (see the connector pinout found in Pmod USBUART Reference Manual). In order to implement the linux UART communication, please take a look on the UART linux example provided by Digilent. It uses the AXI UartLite IP in the Vivado project. This is implemented on Zybo Z7-20 board but it will be easy for you to port in on Zybo Z7-10 board.
  3. Yes, you are right, although you are not confident. That's the way to do it. Add the missing states (S4 - S7), ensure proper transitions (Transitions process), ensure that Outputs proper selects the desired state (Outputs process), enlarge the dimension of signal s to 3 (2 downto 0), ensure proper segments selection for each state (what is now "2-to-4 decoder with active-low inputs" make it "3-to-4 decoder with active-low inputs".
  4. Hello, All the segments from any digit (0, 1, 2, 3) have common anode signal and individual cathode signals (CA, CB, ... , CG, DP). Accessing the segments of the Seven Segment Display is done for each individual digit (0, 1, 2, 3) by selecting its anode and setting the cathode signals (CA, CB, ... , CG, DP) for each segment according tot he information you want to display on that digit. Cycling rapidly (faster than the eye can notice) between the 4 (n) display units creates the visual impression of all the digits being accessed simultaneously. Please read more on this matter on Seven-Segment Display chapter of the Nexys A7 reference manual. Moving from 4 digits to 8 digits will require you to modify the way digits are cycled. By looking into the serializer.vhd code you sent I can notice that this code is already prepared to deal with 8 digits, still only 4 are used (see how the Multiplexer is implemented on 3 bits). Please try to understand how serializer.vhd is implemented. Good luck.
  5. Hello, You will have to sign a NDA in order to get this file. I can organize this (put you in contact with the person in charge), if you agree. So I wait for your answer.
  6. Hello, The measurements posted above show that the user calibration improved the measurements precision. Regarding the question marks you got in the calibration messages, unfortunately I am not in possession of the complete hardware needed to replicate this issue. We will take a look on this one when we will have the opportunity. Thank you for revealing this issue. Best Regards, Cristian Fatu
  7. Cristian.Fatu

    Pmod Mic3

    Hello, If you take a look on the PmodMic3 resource center page you will find this link: Getting Started with Digilent Pmod IPs. This is a good point to start in order to understand how to use Digilent Pmod IPs. Best Regards, Cristian Fatu
  8. Hello, I am trying to help a little bit by answering some of the above mentioned questions / concerns. During factory test, each DMMShield is individually calibrated. The resulted calibration coefficients are stored in the factory calibration area of the non volatile memory of the DMMShield and also in the user calibration area of the non volatile memory of the DMMShield. So user calibration is identical to factory calibration at the factory gates. At any time, the user may chose to calibrate the device. The result of user calibration is only stored in user calibration area. At any time, the user may choose to restore the factory calibration. This means that the data from the factory calibration area is written in the user calibration area of the non volatile memory of the DMMShield, thus restoring the situation from the factory gates. I have two major concerns: 1. (the obvious one) Why does your module provides poor results even after factory calibration is restored ? How do you know that restore factory calibration was completed with success ? 2. Why do you mention that after performing calibration (calling DMMCalibP, DMMCalibN and DMMCalibZ) no data is saved in the Eprom when calling DMMSaveEPROM. For both of my concerns, my question for you regards your working environment. I understand that you use Arduino. Here are some questions that might help us understand what's going wrong: - which board are you using ? - are you using the command interpreter provided by Digilent or your own code, calling Digilent library functions ? Best Regards, Cristian Fatu
  9. Hello, Be happy that the problem was solved that easy. You are welcome, Cristian
  10. Please be sure to insert the USB cable in the proper way. From your picture it seems to me that the cable might be inserted in the wrong way.
  11. Cristian.Fatu

    Eclypse-Z7 ADC demo

    Now it's clear for me and you are right to be concerned. We apologize for this inconsistency. Yes, we stick to the 2^14 - 1 value, and we consider any other value to be wrong. We will correct this information where it is posted wrong. Thank you again for you interaction.
  12. Cristian.Fatu

    Eclypse-Z7 ADC demo

    Hello @Zigot, Maybe I am not correctly understanding your question, I answered this when you asked it in your previous posts: Please give me more details if my answer is not matching your question.
  13. Cristian.Fatu

    Eclypse-Z7 ADC demo

    Meanwhile, starting from your suggestions, I have pushed a version of libraries that limits the buffer size to the maximum value supported by the IP (0x3FFF). Also, I made a test by modifying the demo (in the local repo) to also display the channel 2, modified the buffer length to the maximum one (0x3FFFF), and everything looks good. Thank you again for the cooperation.
  14. Cristian.Fatu

    Eclypse-Z7 ADC demo

    Hello @zygot, You should be able to acquire 2^14 - 1 (0x3FFF) samples on both channels (32 bits of buffer).
  15. Cristian.Fatu

    Eclypse-Z7 ADC demo

    I don't understand how you came to the conclusion that we are only acquiring one channel. The demo only displays one channel data, the trigger only triggers on one channel. Still, the data acquisition is performed on both channels as the buffer width is 32 bits and provides data for the both channels.
  16. Cristian.Fatu

    Eclypse-Z7 ADC demo

    Hello, Our initial concern was that your ZmodADC1410_Demo_Baremetal demo was not working as it should. I tried to explain what it is supposed to do, mentioning that the demo functionality is very simple. From your last posts I conclude that your demo is working. I am not sure about the meaning of the images you provided in the previous post, but seems to me that the reconstructed waveform is correct, right ? Yes, we have analyzed the meaning of the data. We have applied sine and rectangle waveforms on ZmodADC inputs, imported data into excel and the data was good. Regarding the buffer size you are right: I will limit the size to the maximum size allowed by the IP. Thank you for your effort and for this communication.
  17. Cristian.Fatu

    Eclypse-Z7 ADC demo

    Hello, In this moment we try to figure out why your instance of the demos doesn't provide the expected output on UART. That's why we did the following steps (as described in the user guide) on more computers: 1. cloned the demo workspace: 2. start the Vivado 2019.1 SDK, select workskspace location as the downloaded location folder. 3. Program the FPGA 4. Run the ZmodADC1410_Demo_Baremetal demo, with no changes. The output was tested on different terminals (including putty), and looks like this: - value in mV The information is tab separated and consists of: - raw unsigned 14 bits value as it is got from the ZmodADC IP, shown in hexadecimal - timestamp within the acquired buffer. The samples are 10 ns spaced (corresponds to 100 MHz sample rate). Looking on the information you have posted it looks like you miss the tabs. Please send us a caption of your terminal. The approach with these demos was to provide some very simple data manipulation, suggesting that the user is able to to process the buffer data as he intends. The ZmodADC1410_Demo_Baremetal and ZmodADC1410_Demo_Linux are similar, the differences being: - linux demo doesn't display raw data - linux demo writes the formatted information to a text file, to be visualized later or to be imported in excel / waveforms, for example. Unfortunately the maximum buffer length is 2^14 - 1, as this is the maximum buffer size in the ZmodADC IP.
  18. Cristian.Fatu

    Eclypse-Z7 ADC demo

    Hello, It is not clear which platform have you used (Baremetal / Petalinux). The demo projects are posted on zmod_adc_dac/master branch of this repository: https://github.com/Digilent/Eclypse-Z7-SW.git. The ADC Demo performs repeated acquisitions on Channel 1 and sends formatted data over UART (additionally saving the data to a file in Petalinux). In both platforms this is done by calling in main.cpp the adcDemo function. Unfortunately for petalinux the call the adcDemo was commented due to our mistake (we apologize for this). Now we corrected, so you can clone again the demo project.
  19. Hello, You should be able to run the Baremetal ADC and DAC demos from Windows. First of all, you don't need to create the Vivado project in order to run these demos, as the provided SDK workspace contains the exported handoff file: download the provided SDK workspace in SDK Environment import the projects from the downloaded location program the FPGA using the design_1_wrapper.bit file from the in the design_1_wrapper_hw_platform_0 folder you should be able to run the ZmodADC1410_Demo_Baremetal and ZmodDAC1411_Demo_Baremetal demos (eventually recreating the bsp sources in the corresponding bsp projects) Still, if you want to create the Vivado project, it is available on this location: I was able to create the project using the instructions linked from github project readme. The block design looks like this: Regarding my previous post, please ignore my advice to remove .Xilinx directory. You should only remove .Xil directory, if exists. Please tell me if you still encounter issues with these demos. Best Regards, Cristian
  20. As I mentioned in the previous answer on the separate topic: Here is a demo that only uses PL using the low level Zmods IPs: https://reference.digilentinc.com/reference/programmable-logic/eclypse-z7/low_level_zmod_adc_dac There are two use cases suggested when working with the Zmod IPs: carrying out all processing in the PL (this involves HDL code development only) or dividing the tasks between the PL and PS. An example of how to use the Zmods in PL only designs can be found in the above linked demo. In case you need to connect the Zmod IPs to the processing system, our Zmod ADC 1410 AXI Adapter IP can not be currently used for the purpose described (periodic sample transfer to PS). You will need to develop your own IP with an AXI interface (probably AXI Lite will work fine with low sample rates) a a bridge between the PL and the PS.
  21. Yes, it is possible. Using two ZmodADCs will ensure that you can use 3 channels (from the total of 4 available). Regarding the sample rate, sampling at 50 ms here are some thoughts: The IP is sampling at 100MSPS, which is one sample at 10ns. Because you only need 50 ms sampling (which is multiple of 10 ns) you should only keep one sample out of 5000000. This can be easily implemented using a counter.
  22. Hello, Are you using Vivado 2019.1 ? Which OS are you using ? Are you using Ubuntu ? If so, please remove the .Xil and .Xilinx directories from the user home directory.
  23. Hello, The maximum sample rate for the chip on ZmodADC1410 (AD9648) is 105 MSPS and the IP is designed for 100MSPS. This is the only available reference design. What sample rates do you need?
  24. Hello, I understand now what is your expectation. We will try to find an answer for this question too.