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Cristian.Fatu last won the day on September 9

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  1. Although I would also suggest using an Artix 7 solution (like the one James suggested), if you still want to use the old CoolRunner || you should be aware that you can use the Adept application to program bit file to the board, instead of XIlinx tools (Impact). But you still need the Xilinx tools (ISE) to build the bit file.
  2. Hello, The PmodAD2 communicates over I2C protocol with the main board on which the Pmod is plugged. The PmodAD2 has no UART / USB capabilities. It is the main board that communicates - using its USB-UART capability - with the PC. Connecting the board using a USB cable creates a COM port on the PC. When you open a TeraTerm (or other terminal) connection, you select the COM port. Therefore a possible approach could be to have 2 PmodAD2 connected to a single main board, in different Pmod connectors. The SDK application should gather the AD2 data (measurements), format a text message containing these measurements, and then sending the text message over UART to the PC, to be later visualized in a terminal. What application are you running on the FPGA board ? You should modify it to read the other Pmod as well.
  3. Hello, Being a FPGA, you can use most of the FPGA pins to implement IO operations. For example, you should decide to use some pins of a Pmod connector. You should edit the xdc file, uncommenting the lines for these pins and maybe assigning user friendly names to the pins. If you are using VHDL, please take a look on Basys3 General IO example. The GPIO_Demo.vhd component is responsible for dealing with GPIO signals. The buttons are considered input IO signals, while the LEDs and considered output IO signals. Good luck.
  4. In order to communicate with PmodGPS, UART communication is required. In order to communicate over UART, we should rely on a linux driver that implements UART. In order to get this driver in your linux image, you should include the UART Lite IP core in your hardware design. You will notice in the ./components/plnx_workspace/device-tree/device-tree/pl.dtsi axi_uartlite_0: serial@42c00000 { clock-names = "s_axi_aclk"; clocks = <&clkc 15>; compatible = "xlnx,axi-uartlite-2.0", "xlnx,xps-uartlite-1.00.a"; current-speed = <9600>; device_type = "serial"; ... } After building the petalinux image and booting the zedboard, you should have the /dev/ttyUL1 device which is the UART Lite linux driver. Then, your application should access it in order to communicate wih the PmodGPS. I have created a hardware platform that provides the basic UART communication. See and the provided that explains the basics of this approach. It also provides a demo linux application that communicates over UART (included as submodule). If you intend to communicate with PmodGPS, you should take a look on the PmodGPS standalone (baremetal) driver provided by Digilent vivado-library repository. There, you should implement the UART communication by calling the function provided in the UART application. As mentioned in the, you should swap the uart_rtl_txd and uart_rtl_rxd as the posted application is intended to be used with PmodUSBUART. Please write me if you have questions.
  5. Hello, Please read the library pack user guide. On the ADC, MIC, AUDIO modules descriptions you will find more details. The analog to digital conversion is done on 10 bits, as they are performed through analog to digital capability of PIC32. See PIC32 datasheet for more details.
  6. In the context of your initial question, I have built a simple MPLABX project for Pro MX7 board that just blinks a LED. I used Pickit3 connected to JP17. Please note the ICESEL pragma config. Good luck, Cristian Fatu
  7. I agree with James, there are poor chances to implement a proper oscilloscope with this DMM device due to its poor acquisition rate. To check this, you could modify the provided demo and remove the delays from the main loop, so you can see data acquired at maximum rate.
  8. Hello, As you noticed, this multiplication factor applies to the value acquired from AD converter. It encapsulates the converter gain, the converter maximum value (2 ^ 24) and a scale factor. This factor should be considered as a whole. After applying this multiplication factor, the acquired values are corrected using the two calibration factors (additive and multiplicative).
  9. Hello, We are happy that you enjoy Zybo Z7-20 board. The heatsink part is Malico BHBH3119191300-07.
  10. Hello, Please check to have the POWER jumper (JP2) set to USB and the POWER switch (SW16) set to ON.
  11. Hello, I can't give you more details about Multisim, still your question seems to me to be independent to Multisim. You should take a look in the constraints file (xdc) which is specific to each board. Here you can find more details about Vivado constraint files. Here you can find the Nexys 4 DDR constraint file. Please tell me if I can give you more details.
  12. Solved, wrong JP3 jumper configuration.
  13. Hello, We found this part number: CSD-11-A0000. In case you want to look for alternates I am sending in a message the component datasheet.
  14. I wrote you a message requesting more details about this problem.
  15. Hello, Nexys 3 being a SpartanĀ®-6 FPGA board is not recognised by Vivado. So you should focus to the ISE related materials from Pmod OLED resource center page: Nexys 3 Verilog Example - ISE 14.2 Nexys 3 VHDL Example - ISE 14.2 Still, here is an answer to your question: Unfortunately the information from file for the Vivado project is not right. We aplologize for this. You should download the release (click on "1 release"). In order to create the project, you should run in vivado the create_project.tcl script (after changing directory to proj). Good luck.