seaover

Hello Eduard, Fortunately I found that post some days ago. I fixed the Makefile file under 4 folders in my platform project for application project. The link for answer record is right solution. Thanks so much.

Hi, I am a new comer just start studying FPGA with Zybo Z7-20 with Vivado 2020.2 and Vitis 2020.2. Tutorial, Creating a Custom IP core using the IP Integrator (https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-creating-custom-ip-cores/start), is a good resource to study the Custom IP for the first time. I followed all the procedure and got to succeeded exporting the hardware by going to File -> Export -> Export Hareware.... Of course, I included bitstream when exporting. Then I select File -> Launch SDK. I choose "C:\FPGAprojects\ZYBO_Z7-20\PMW_AXI_tutor\PMW_AXI_hw.sdk" as workspace for Vitis 2020.2 Then I made an application project successfully with the exported hardware from Vivado 2020.2. I set Repository as "C:\FPGAprojects\ZYBO_Z7-20\PMW_AXI_tutor\PMW_AXI_hw\PMW_AXI_hw.ipdefs\My_PWM_Core_1.0" by selecting Xilinx -> Repositories -> Software Repositories. Then I make right-mouse-click on platform project, design_1_wrapper, and select Build project. Unfortunately project build fails due to some kind of compilation error. Messages in "Message_in_Console_view.txt" are copy of messages in Console view, generated during project build. When I navigate the folders/files in platform project after project build finished with error, the files/directories structure are broken, compared with normal cases. To help understand the case, I want to upload my zipped project files. But its size almost 31MB. If it is needed, please let me know. I attached one message file: 1. Message_in_Console_view.txt messages in Console view during platform project compiling I tried to solve this problem almost 2 weeks. But, I failed. Could you kindly advise me the way how to solve it ? Many Thanks in advance, HaeSeung Message_in_Console_view.txt