Pavel

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  1. Dear administrators, Could you please explain to me how to delete my account and all my messages from this forum? I've already looked for this option in the settings of my profile and in the frequently asked questions but couldn't find it. It would also be great if you could delete comments containing insults and unfounded accusations and at the same time containing my name: link, link, link, link, link, link, link. Best regards, Pavel
  2. It would be great if Digilent has created a Pmod module based on an audio codec with an integrated amplifier, such as for example CS42L52, that can directly drive a speaker. Unfortunately, the only Pmod that could be qualified as a codec Pmod that I could find is Pmod I2S2. Its output part is based on CS4344 DAC without any amplifier. Since @Tim77 wants to avoid adding an amplifier and wants to output monotones of notes of a musical scale, I think that Pmod AMP2 better matches the requirements than Pmod I2S2. BTW. It would be interesting to check the sound quality of Pmod AMP2 i
  3. Here is a link to an article by @[email protected] explaining how to use Pmod AMP2: https://zipcpu.com/blog/2019/04/24/pl-pmodamp2.html I think Pmod AMP2 should be able to drive small speakers more reliably than a single pin on the Basys3 board.
  4. Just found a driver that enables user-space configuration of the PS-PL clock: https://github.com/ikwzm/fclkcfg I think this driver is the cleanest solution to this problem.
  5. During the boot, the PS-PL clock is configured by the First Stage Bootloader (FSBL). If the FPGA configuration used to generate the FSBL code has the clock active, it will be activated during the boot. Otherwise, the PS-PL clock remain inactive. I think it should be possible to enable the FPGA clock fclk0 and set its frequency from the Linux command line using the following commands: devcfg=/sys/devices/soc0/amba/f8007000.devcfg echo fclk0 > $devcfg/fclk_export echo 1 > $devcfg/fclk/fclk0/enable echo 100000000 > $devcfg/fclk/fclk0/set_rate It's also possible to do it fr
  6. I think the pins of the Basys3 board can output enough current to drive only a very low power (0.2-0.5 W) speaker or a piezo buzzer. I'd say the easiest way to make some basic sounds is to use a piezo buzzer that can be directly connected to the pins of the Basys3 board. To get an idea of the sounds that can be achieved this way, here is a link to a tutorial showing a piezo buzzer connected to a pin of the micro:bit board: https://www.hackster.io/anish78/piezo-buzzer-with-bbc-micro-bit-b0fc27 At the very end of this tutorial, there is a video showing the result. The sound q
  7. I'm very surprised to see this kind of reaction to my initial answer and my additional comments. Let me try to explain one more time why I think my initial answer is not wrong. Here is the description of the setup from the original question: Nexys-4 DDR board 200 MHz oscilloscope x10 probe The original question: I think the problem is trivial and there is no need to introduce any additional complexities to model it. We basically have a capacitor (the oscilloscope probe and the oscilloscope input) periodically charged and discharged with a limited current
  8. My recommendation was not a general statement and the context was very well defined: Nexys-4 DDR board, 200 MHz oscilloscope, x10 probe. Here is a link to an application note explaining how drive strength affects the edges of the signal: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an476.pdf Figure 3 on page 5 shows a pulse with three different drive strength settings. Here is a copy of this figure: I think it shows clearly enough that increasing the drive strength can help make the edges of pulses sharper.
  9. Here is a link to an interesting comparison of signal edges for different connections between the signal source and the oscilloscope: https://www.edn.com/sharpen-rising-and-falling-edges/ Even in the worst case the peak-to-peak rise time is less than 5 ns. So, it should be possible to obtain sharper edges than shown in the original question even with a pretty generic probe. I can obtain 5 ns peak-to-peak rise time on my 200 MHz oscilloscope without any effort. However, I've just checked the schematics of the Nexys-4 board at this link and I see 200 Ohm resistors connec
  10. I have a project that has FFT connected to CORDIC: FFT (radix-2 lite, fixed point, unscaled) -> AXI4-Stream Data FIFO -> CORDIC (translate, word serial) This combination works well for me. With the CORDIC's architectural configuration set to 'word serial', the utilization of the FPGA resources by the CORDIC IP core is quite reasonable. I also use other DSP IP cores (DDS, CIC, FIR, complex multiplier) provided by Xilinx. They help me make quite complex systems by simply connecting their AXI4-Stream interfaces. I'm afraid that if I had to write similar IP cores myself, it would
  11. I'd suggest checking the parameters of the pin that outputs this signal. I think that setting Slew Type to FAST and Drive Strength to 8 or 12 should help make the edges of pulses sharper. In Vivado, the parameters of the pins are accessible via the I/O Ports window (RTL ANALYSIS -> Schematic -> Window -> I/O Ports).
  12. Thank you for clarification and for updating your comment.
  13. I might be missing something, but I've tried to implement most of the user controllable features of Zmod ADC and Zmod DAC. The signals for the relays are implemented, the SPI commands are also implemented, the dpmutil program is present. Maybe they're not implemented in a way as you would have done, but that does not mean they are missing. I can only think of one or maybe two small features that I haven't implemented, but I think they're insignificant. Anyway, when you're writing "many", I think you're exaggerating. Please let me know what is missing.
  14. Not at all. My point is that @ebaser has already Eclypse Z7 and I try to help him understand how to use it more or less optimally. Otherwise, I use a lot FX2LP+MAX10, but it's not the subject of this thread or even of this forum. So, I apologize for this short off-topic.
  15. It's not a good idea to send the data from one FPGA module to other FPGA module via the CPU. DDS and DAC should be directly connected inside the FPGA. If you're interested I can send you an example showing how it should be done. The XEM-7320 board has almost the same FPGA as Eclypse Z7 only without the CPU. So, it'll enforce you to connect the FPGA modules directly. If you want to change the board, then I'd suggest switching to ADALM-PLUTO. ADALM-PLUTO has an on-board GHz transceiver that would simplify the analog part of your radar project.