I'm trying to initialize my design's block memory content, so that after the synthesis process and bitstream generation, the FPGA will boot up with some specific data in its memory cells. The BRAM I'm using is generated using the standard IP Block Memory Generator v8.2. The BRAM size I'm using is relatively large, about 128 Kbits, so my preference is to manually determine only the values of some portions of it. Is there a practical automated way to achieve all this in Vivado? Using Vivado, my initial approach was to use the "Load Init File" option in the IP generator dialog, and use a coe file. However, this did not seem to have any effect once I programmed my Basys 3 board, I'm suspecting that coe files for initialization are not synthesizable. Is this true?