ntrstd11

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Everything posted by ntrstd11

  1. I'm using two inferred RAM modules which are assigned an initial state by reading lines from a file, as suggested to me previously here, in VHDL. The setup works fine, and all the RAM contents are loaded during synthesis properly. However, as my design is pretty large, it takes a lot of time to synthesize the project each time I need to only change the RAM initialization files. I need to synthesize very often while testing with different memory contents, my design being otherwise the same. Is there a way to only modify the memory contents of a design without having to synthesize the whole project? I tried using incremental builds but the improvement was not that effective.
  2. I'm trying to initialize my design's block memory content, so that after the synthesis process and bitstream generation, the FPGA will boot up with some specific data in its memory cells. The BRAM I'm using is generated using the standard IP Block Memory Generator v8.2. The BRAM size I'm using is relatively large, about 128 Kbits, so my preference is to manually determine only the values of some portions of it. Is there a practical automated way to achieve all this in Vivado? Using Vivado, my initial approach was to use the "Load Init File" option in the IP generator dialog, and use a coe file. However, this did not seem to have any effect once I programmed my Basys 3 board, I'm suspecting that coe files for initialization are not synthesizable. Is this true?