Zakir Hussain

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About Zakir Hussain

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  1. Hello everyone, I have been trying to interface JTAG HS3 + JTAG UART with Adalm-Pluto using Xilinx vitis. I have exported .XSA file for zynq zc010 and tried to build an standalone application for simple Hello World program, but I'm facing an error while i try to debug as lauch hardware. I faced the following error. Error while launching program: fpga configuration failed. DONE PIN is not HIGH
  2. Hi im getting these warnings while i try to validate design in Vivado while executing hello world program which makes use of Zynq 7000 boards. i kindly request you to give a siolution for these warnings [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values. [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values.