ebaser

Thank you for the detailed explanation, I got most of the points. I don't have to use the UART, I was just thinking if it is the way to do it. As you said, sample rate of the UART will not be sufficient. USB or UDP may work but I don't know their details & how to implement them.

Thank you, I haven't seen your project before, I'll take a look it asap. Unfortunately, I've bought Eclypse Z7 and have no chance to change it. For the rest, I'm a little bit confused about the serial communication part. Isn't it same with using JTAG&UART Micro USB port on the board to communicate? Also I'm not sure if I can handle an external memory connected to the system to store&manage data.

Hi @Ciprian, Thank you for the suggestion. To briefly explain, I'll produce some sweep signal periodically from DAC and capture the reflected signal with ADC port and send it through UART to process&visualize it on my PC. If I use the Low level example, how can I send this data through serial channel without PS? I've coded UART in VHDL with a state machine model in the past but I'm not sure if I can integrate each other. Current working diagram in my mind is like as shown in below.

Hello, I've been dealing with the demo projects that digilent provided for Zmods since last week. My aim is to develop a FMCW radar application using both ADC and DAC. From the screenshots on below, I figured out the basic working principle that; for DAC; A buffer in DMA for the DAC is filled from the DDS output, then it is read from the DAC module and sent over the controller. For ADC: when I call the function start.adcZmod on software, it starts to fill the analog data to a buffer on it's DMA. But the part I don't understand is how it works when it comes to real time data processing. FMCW needs precise timing, so I need to start ADC immediately as the chirp is produced from DAC. The maximum length of the buffers in DMA are 0x3FFF(16383 in decimal) as I understood. So, if I produce a sweep, will the maximum time interval of it can be 163,80us maximum since the clock frequency is 100MHz. Secondly, what can I do if the incoming wave is not fitted in one buffer? I'm a fresh graduate and trying to develop my skills on FPGAs and signal processing. Thanks in advance.