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Gopal Krishna

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    Gopal Krishna reacted to zygot in ethernet port access of FPGA   
    Here are two that you might find interesting:
    https://forum.digilentinc.com/topic/1985-arty-sending-udp-packets-without-any-software/
    https://forum.digilentinc.com/topic/3968-ethernet-udp-echo-server/
    There are a few more. Hamster posted some links to a website that is now non-functional so I can't reference them. That's a problem with posting links instead of project code.
    If you just start googling you will eventually find the right keywords to find interesting projects with source.
    https://github.com/dawsonjon/Chips-2.0 once published an interesting UDP demo with source code... and odd but weirdly interesting approach to using C to implement verilog in FPGA BRAM. 
    Talking is easy. I know more than a few people who seem to be able to do it without any thought processes going on in their head. Listening, that is not only hearing, but processing and understanding what you hear, is far more difficult and less common in human to human conversations. The same applies to Ethernet. It's really not hard to broadcast or send a specific packet type to an address using HDL. Parsing incoming packets, detecting packets is starting to be a bit more involved and require more work. If you want to do point to point data transfer this isn't all that difficult using and HDL. If you want to go through a switch or router, then there is more complexity. If you want to make your FPGA look like a PC running a modern OS and handle fragmentation, out of order packets, error conditions, re-sending missed packet and such then implementing this using logic starts getting very complicated. You could use a soft processor core in a regular FPGA to do this but the task will still involve a lot of work.. even if you ignore security concerns. For a typical ZYNQ board an Ethernet application is just software. Even this isn't trivial unless your ZYNQ is running some highly tailored and reduced version of Linux. The problem with the OS solution is that Ethernet is usually handled by system processes. Ill-formed packets might never be handled. Running Linux on a typical FPGA board in a way that is satisfactory isn't necessarily easy to do.
    Anyway, the two projects that I provided links to can help you get started. Fortunately, Ethernet isn't proprietary so you can get standards and information about protocol and packet structures from the internet.
  2. Like
    Gopal Krishna reacted to zygot in ethernet port access of FPGA   
    With regard to partially functional demo cores supplied in netlist form please do report back with how that worked out for your needs.
    If all you want to do is have your FPGA application spit out UDP packets then you can find some nice example projects with code sources in the Digilent Project Vault.
    Demos are one thing. Demos that allow the user to create their own custom application is another thing. Having the source code so that you can implement a full blown application for any FPGA target is another thing altogether.
    I should point out that I have no opinion on the capabilities of above mentioned Ethernet cores. I've not paid for them, nor seen any benefit to trying out one of their demos that would be worth my time.
  3. Like
    Gopal Krishna reacted to PhDev in ethernet port access of FPGA   
    I have been using the Ethernet cores from FPGA-Cores.com for a couple of years now and they work without problem. They contains all you need to connect your FPGA to Ethernet. Really simple to use. No processor needed. They are free to download.
    There is a tutorial  Nexus board here.
    It is only possible to use these cores when the phy is connected to PL on the Zynq devices.
  4. Like
    Gopal Krishna reacted to zygot in ethernet port access of FPGA   
    The ZC702 Ethernet connector and PHY is attached to the PS in the FPGA. If you are using Vivado 2019.1 or earlier the SDK has example projects to help get you started. In this case the MAC is in the PS.

    The Nexys A7 has an external PHY but you have to use MAC IP. This isn't free for recent versions of VIvado. If you look around you might find open source MAC source deo that might be suitable for a project.

    There are two ways to transfer data from an FPGA to a PC. One is using a MAC and a full Ethernet software stack to handle all of the packet detection and parsing, and conditions. If you want real Ethernet connectivity then you will have to do a bit of software design. There's really no way around understanding Ethernet protocol and this is complex.

    All of my designs for FPGA <--> PC communication using the Ethernet port use the PHY as a modem and don't include a MAC so they use FPGA devices without the ARM or soft cores.

    I wish that this was a easy thing to do, but you can look around in the Digient project vault so see what's available, or search the web for design examples. This just isn't anything available that makes using Ethernet on an FPGA as if it were a PC simple. That isn't to say that you can't find code and projects to do simple communication.

    Even simple Ethernet isn't simple. If you want to connect your FPGA board to a LAN or the internet safely, it's very hard and complicated. There's no easy solution that I know of. Year ago people made products to add Ethernet connectivity to embedded designs but even these ended up not always being trivial for full-blown applications.
  5. Like
    Gopal Krishna reacted to zygot in ethernet port access of FPGA   
    Xilinx FPGA devices ( except for ones with a hard processor like ZYNQ )
    don't have an Ethernet port, but perhaps your FPGA board has an Ethernet PHY.

    You certainly can use an FPGA board with an Ethernet PHY to communicate with a PC. The PHY interface to the FPGA can be complicated and require advanced FPGA skills. Regardless, you will need to do some software on the PC side and possibly on the FPGA development side, depending on your design flow. Most people would take what appears to be the easy path and use a MicroBlaze centric design ( I didn't ask but assume that you don't have a ZYNQ based board ). I can't help you with MicroBlaze. If you do have a ZYNQ FPGA board then the Ethernet PHY and MAC are built into the FPGA PS complex.

    For ZYNQ boards there's no logic design and you can try your luck with any of the OSs supported by the tools. The tools support the Xilinx standalone OS, Free RTOS, and Linux. As far as I know Linux development for Xilinx FPGA tools still isn't integrated. So, you need to install Petalinux or, if you are brave try picking a flavor of your favorite Linux distribution and try doing development that way.

    Now that I've said all of that I suspect that your question is a homework assignment...


  6. Like
    Gopal Krishna reacted to zygot in PMOD AD2 interface with atlys (Xilinx Spartan-6 LX45 FPGA) board.   
    Digilent has support for the PMOD AD2 in the vivado-library repository in GitHub. This may or may not be useful as is, but there is source code to work from. It's always a good idea to check out current Digilent support for it's PMODs. Not all PMODs have any support. The Digilent PMOD AD2 product site here: https://reference.digilentinc.com/pmod/pmodad2/start also has links to other project sources, such as those by ADI. ADI has good FPGA support for a number of its products suitable for Linux hosts.
    You should get the datasheet for the AD7991 from the Analog Devices and read through it even if you don't intend on doing substantial HDL development on your own. It's always a good idea to understand how your hardware works and what its limitations are.
    In general demos and other available published project code for particular hardware has limited usability for user applications unless you are prepared to do some HDL work.
  7. Like
    Gopal Krishna reacted to Luke Abela in Ethernet Communications in an FPGA   
    Good day,
    I am currently working on a system which requires ethernet control on an FPGA. To this extent I have successfully managed to implement the echo server as per Xilinx`s tutorial. However, I now require to transmit data from my laptop to the FPGA. I am unsure of how to amend this project in its current state to receive data from an external program (such as matlab) and from where to verify the data I have received is correct. Could anyone kindly provide some insight? Regards
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