Gopal Krishna

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Everything posted by Gopal Krishna

  1. @zygot thank you for your kind suggestion. Can you please provide me link of example project, I am not able to find it.
  2. Thank you @PhDev I will try to implement.
  3. Thank You Very much @zygot
  4. Thank You @zygot for your reply. Fact is that I am very new in this FPGA world . I have done some small learning project on FPGA using Verilog and VHDL code. Now I am wondering how to access all these external ports available in FPGA(Ethernet/ USB/ HDMI). I have ZYNQ FPGA (Xilinx Zynq-7000 SoC ZC702 Evaluation Kit), I have Nexys A7 board also boyh has ethernet ports. I have tried to design ethernet protocol using Verilog but It seems very complex. I believe if port is available there must be some way to communicate with PC using ethernet port. If you know how to do it t
  5. How can I access Ethernet port of any FPGA to transfer data from PC to FPGA and vice versa.
  6. Hello Recently I have purchased Digilent PMOD AD2. I want to interface PMOD AD2 with my Xilinx Spartan-6 LX45 FPGA board. For conversion of analog signal into digital format. Could you please help me to do this. should I have to write HDL code of I2C? what is maximum speed of operation of PMOD AD2? -- Thank you Gopal Krishna
  7. Dear all Please help in accessing ethernet port of Atlys FPGA board. Is it possible to access ethernet port using available IP in ISE or I have to write protocol for it. please reply if anybody has done that. -- Gopal krishna
  8. Thank you @JColvin Thank you very much for your reply, your earlier post regrading PMOD DA4 was really very helpful. NOW my DA4 is working fine with Atlys FPGA. Do you have any idea about how to configure atlys FPGA ethernet port to transmit and receive data from computer?? -- Thanks Gopal
  9. I am trying to interface PMOD DA4 with atlys FPGA but nothing is coming at output. help me to rectify what wrong with code. module spi_master_v1( input sys_clk, input rst, output reg cs, output reg MOSI, output reg sclk, // input [31:0] in_data, output reg done ); // Internal registers reg [10:0] count; reg [31:0] temp_data; reg [5:0] bit_count; reg [11:0] count2; // state declearation reg [1:0] state; parameter idle = 2'b00; parameter data_tx = 2'b01;
  10. How to interface ethernet port of spartan 6 Lx45 FPGA board with LAN wire?