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  1. hii @zygot thanks for reply yes, you are right about the zybo board, but i'm only looking for simulation, in simulation part i'm able to do calibration but after that MY OUTPUT data is shifted why it is shifted that's my question. (screenshot7) as per me it is some clock/time issue, cause memory might get different value at different time (what's that time? i don't know) my mig works at 400Mhz and ddr3 at 800Mhz with data bit width of the user side 16*2*4==128 bits. and one more this for this i need to keep hi_pri signal high, otherwise my app_rd_data give some values
  2. hello, i'm trying to simulate the mig controller to test calibration>write>read operation. i'm using MT41J128M16xx-125 memory and ZYBO-020 board. in simulation calibration is complete at 104us (nit_calib_complete =1) but and not able to receive the input data (app_wdf_data[127:0]) at the output pin (app_rd_data[127:0]) i check the vivado design example, in that also output data is random (as per me). so anyone please help me with this what've i done so far:- instantiate the mig_7series_0 in a top module copy the sim_tb_top (test bench in example design) an
  3. hello @rappysaha and @[email protected] is there any progress in this question. i'm also working with MIG7 to communicate with ddr3, while doing so im able to get init_calib_complete signal high and all other signals correctly also but not able to write and read the required data. i simply instantiate the mig ip in a vivado testbench example. @rappysaha where you write this above mention code (in testbench?) and is it work(you received the data correctly from the addr) and @[email protected] will you please elaborate this "Be aware that it takes quite a bit of time for the MIG to start up