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  1. aams

    Pynq Video Processing

    thanks for replying, i added a constant one to connect to reset of video to Axi4 and Axi4 to video. 1. this design uses axi stream subset converters, right after: video in to AXI4, and right before: axi4 to video. even though input and output both have three bytes. I dont understand why they are there.. zybo_Z7-20.pdf
  2. aams

    Pynq Video Processing

    Hi everyone! I am trying to create a design on Pynq, in which 800x600p video would be streamed in through HDMI. This would be stored in DDR memory. And to verify the saved data, the same would be streamed out on HDMI. 1. I have made a block design. i think this would be the blocks needed for the design. I have attached the PDF of the design. does anyone think I'm missing anything. 2. I think there i have made all the necessary connections, I have left a few resets unattached, would those be a problem? 3. How do i go about writing software for the design, this is something I d
  3. this project to be specific. Are there any pitfalls I should avoid? https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-z7-hdmi-demo/start
  4. hi, I am trying to make a simple design that drives an hdmi display, but I get nothing on the display attached is block diagram, clock wizard generates 40 MHZ. for 800 x 600. same is reflected in default section of VTC. RGB2DVI is set for less than 80 MHz, with serial clock generated internally from pixel clock. using Vivado 2017.1. The video patters generator is a very simple IP that streams out color bars, written in c using hls. This was working with ZEDboard. I have generated a new project for hls, with xc7z020clg400-1 part number just to be safe. I can upload the pro