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  1. Sure. As start, open vivado and in the language templates you can search for xadc. You will find a snippet for verilog instantiation. I do NOT claim to understand it right away. See UG480; it includes a more elaborated example. Uhm, are you sure your platform project compiled correctly? How did you get there?
  2. Thank you Zygot, honestly I couldn't believe my findings I hoped really there could be another way (but I knew since start your suggestion made sense!). Yes, I agree. I'm trying various things for the time being as I approach a methodology which gives trustful results. It's taking me ages and I often forget things in the evenings but I'll be getting there... at some point 😅 Nonetheless, I already bought a Kria. I am confident its "reasonable" level of performance will satisfy my needs.
  3. I can't help with the USB issue but I sure can help with this. The whole Vivado/Vitis "project" thing is a utter nonsense. I try to convince myself it makes sense on a different mentality but no, "projects" in Vivado are a joke! Vitis is sorta better but I wouldn't say it qualifies as "decent". Don't even try importing anything which is more than a version old, this works only sometimes and the malfunctions can be non-obvious to say the least! Vitis comes with its own examples. When you create your application project, select "TCP/IP echo client" as test. Again, you'll need to fiddle
  4. What are your concerns? As far as I can tell the only difference between the Z10 and the Z20 in the SoC and both use the same architecture and technology, everything else is the same. If your project fits and passes timing on the Z10 fabric it will work. If you use a single thread the CPU code will be the same. OFC it is not a complete 100% guarantee. Those things don't exist in reality. In general, you don't need to really buy to have Vivado (or Vitis HLS) run their magic. If they tell you everything is fine, odds are they are right (except when they're cathastrophically wrong,
  5. Hello Delmas, I would ask: what have you tried? But really, help us help you. What issues are you having? Does the host app compile? Do you get link errors? Something involving makefiles? As far as I can tell, Vitis examples don't even know what boards they'll be running on and they add a lot of useless cruft such as the I2C handshake which shouldn't be there (and it isn't compiled as it's guarded by #ifdefs). Do you get to at least complete PHY initialization?
  6. I think we have managed to find a common point, thank you. I don't know how I will do in other chapters of this book but for the time being, I would be happy enough with putting a stop on this issue. Pulling in the XADC measurement took more effort in finding the documentation than the work itself but the process has been straightforward. The first batch of runs I made passively cooled. I tried: 6 stages, no buffers, 100 Mhz - LUT29% FF30%, Vivado estimations 2.415W, 52.9C. Highest tmax reported 54.7C after about 4 hours. 6 stages, full buffer, 200 Mhz - LUT 29% FF39
  7. Hello Zygot, thank you again for the input. I don't know what to say more than that, your help is invaluable. I need some more time to digest all this content. I feel the need clarify a key thing. There has been a time I when I followed and even advocated for best practices. In my spare time I cannot quite stick to it anymore - just today I got assigned to yet another year-long project which would require a whole team and I'll need to complete in in a few months! I agree with you about power delivery; above I tried to make sense of whatever the power delivery was woefully unreasonabl
  8. ??? I'm not sure I understand those things. Probably because I have a different mindset. First, minor thing: XADC user guide is UG480 (four hundred 80). For the purpose of future readers, I think it is a good idea to document the progress what changed since last time? It turns in the refactor to time 200Mhz I flipped a bit in the 'start work' functionality which would cause the device to almost never transition back to ready state. By itself, this caused the CPU code stall. I took the occasion to rework a bit the thing to be more robust so I could at least run something
  9. Thank you for the pointers, I have been interested in using XADC for long time so I will take this chance to read UG780. It is my understanding bare metal apps run on core 0. I will try rebuilding the Vitis project to run on core 1. I hoped the issue would be about main PSU dynamic response but if both Z7-10 and Z7-20 use TPS65400, then either the -10 variant is hugely overspec'd or the -20 is underpowered. The -20 is thee times bigger! Nonetheless, I have been trying to run some... something very similar to the old device from weeks ago (it has a few thousand extra flip flops b
  10. Erm, I understand those things up to a certain point. I have dumped "fpga DRU" in duckduckgo and found those two links across the garbage. For "XADC in PL logic using DRU", I have found a little more interesting content here and there but I don't quite connect the dots. What does that even mean? Anyway, I guess it is a good idea to take a step back and start from easier things first I've left out some important information. The Arty Z7-20 has a magical green led LD12, labeled "done" it turns on after FPGA bitstream has been uploaded. This is supposed to
  11. Thank you Zygot, I have difficulty boiling down the suggestions to a concrete course of action. For the time being, I notice this: That's a scary possibility! My design pours out a few monitor signals which are fetched to a not-quite-PWM. If memory serves it should be pulsing at about 200khz. It all goes through FPGA fabric. Indeed, the system does poll HW through AXI quite frequently. Assuming no bugs it should happen a few times a millisecond but I am inclined to look elsewhere as in my debug runs I am stepping through manually and it still hangs at dispatch, it neve
  12. Hello, I hope you will be enjoying your vacations if you have been given some. For me this has meant finally being able to work on my spare-time experiment and finally reach closure on my upgraded design. Let me describe the process. The ArtyZ7-20 is just the initial prototyping. I'm going to move to real production FPGA boards ASAP (probably in August) but for the time being I'd just want to go ahead with the Arty. The system is systemverilog RTL and barebone C++. The initial design was 100Mhz and 6-stage pipe. Vivado estimated about 2.2W power. I suspect it was much lo
  13. Hello Sai. I can't quite decode your English so I'm taking a wild guess. You say the zybo has sent data but the PC cannot receive it. Check your UART settings, with some luck they're just mismatched. You might find this useful.
  14. Thank you, I forgot about Tera term. It seems my COM settings were reverted to 9600 somehow. Once I set back Tera Term to 115200 it worked just fine. I'd like to know what happened and how to permanently fix it but all things considered I'll just follow your suggestion, the terminals in Vitis are unconvenient anyway.
  15. I don't know what happened. A few days ago - at the time I was using Vitis+Vivado 2019.2 - I launched a debug session and the Console had no output to be seen. I imagined I selected the wrong console: the zynq seems to export two terminals "TCF Debug Virtual Terminal - ARM Cortex-A9 MPCore #0" and "TCF Debug Virtual Terminal - ARM Cortex-A9 MPCore #1". Bummer. I was on the right console. There was no output anywhere. I checked the settings. At first, I couldn't notice anything wrong. I eventually went nuclear and decided to upgrade to 2020.2. A very bad idea. I eventua