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  1. Hi 😄, It seems there is very less activity on this forum, meanwhile i managed to solve this problem and I'd like to share my success. In a short form this is what my work flow looks like: ------------- Vivado Part 😵 ------------- 1) Create a project with the Zybo board 2) Import constraints file for Zybo and uncomment LEDs, Ports and buttons you need and don't forget the clk clock. 3) Import or write your VHDL or Verilog file (make sure to test your code before trying to upload it to the SPI Flash) 4) Create a Block Design and Add the ZYNQ7 Processing System
  2. Hello, I am not an expert but I noticed on your ZYNQ7 Processing System IP Block that the port FCLK_CLK0 is not wired to the M_AXI_GP0_ACLK port on the same block. Attached is my project screenshot and works perfectly. Once you add the ZYNQ7 Processing System IP Block to your design you need to press on Run Connection Automation link that will be displayed after you add your IP Block. I hope that helps Good luck, M
  3. Hello All, I am not at all experienced in FPGAs, the only thing I did is in ALTERA in bachelor studies course and recently the Xilinx Zybo board and made a LED blink or a full-adder examples. I am however finding it difficult and frustrating to try to program the flash memory in the Zybo board to make my code non-volatile, after many trials and looking at other examples that do not describe this process step by step there is only ending up quitting. i came across things like FSBL (First Stage Boot Loader), along with the bit stream from Vivado project, then i wanted to avoid th