RodRico

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  1. Brings to mind your discussion of FPGA Hell and formal methods on your blog.
  2. @zygot You, know, maybe I'm looking at this upside down. Early in my career, I introduced FPGAs (and DSP) to the subsidiary I worked in. Over time, the number of FPGA programmers increased dramatically. Among that group, I was unusual in my use of hierarchical design using schematic blocks; most folks just made big flat designs. The hierarchical method is, however, the only way to deal with the very large designs made possible with the huge FPGAs of today that are programmed by teams rather than individuals. This should have pushed our tools toward hierarchy, so I went looking for it in the to
  3. Translated into the software world, you've just expressed the motivation behind FORTH. The language is simple but immensely rich, and the development environment couldn't be simpler. I've written incredibly complex applications that are remarkably brief using nothing more than a text editor and the integral interpreter to complete unit and application test. Hello World in FORTH is simply : HELLO-WORLD ." Hello World." CR ; typed into the interpreter/compiler. Once I finish my FORTH core, the whole environment will reside on the board and there won't be a "development flow," just typing the sa
  4. That's good practice, but I'd be happy if they simply got the xdc file and VHDL sync'd up. It's obvious the author didn't actually run the project as posted because all the entries in the xdc file were still commented out except for those associated with configuration. It would also be nice if folks actually made the comments in their VHDL relate to the VHDL. In the demo VHDL, there are comments at the top of the file referring to a seven segment display that doesn't exist on the target and isn't coded in the demo, for example. Part of me wonders if they didn't intentionally set up the demo as
  5. @zygot I don't think it's "rushing" to install a demo provided by the vendor in order to confirm the board works so I can promptly return it if it does not. I run "acceptance test" on everything I buy shortly after I have it in hand. I think most folks do. I'm reading through piles of documentation from Digilent and XIlinx to fix the demo... I'm changing the pin names in the xdc file to match the names and case used in the VHDL while also verifying the named pins correspond to the proper pins in the board file and the schematics to prevent smoking something. The demo I'm trying to run is
  6. RodRico

    Simple Newbie Question

    I just downloaded the Arty S7 CAD file, and can use it to make "negative space" in a cover and base pretty quickly. Thanks for the offer though!
  7. RodRico

    Simple Newbie Question

    Thanks Dan! I'm a Solidworks user, and it won't import SCAD. Do you have an STP or STL file?
  8. RodRico

    Simple Newbie Question

    I did. I always do. I do not, however, read everything as thoroughly as I do once I have the product in hand and am trying to use it. In this particular case, it's a simple mater of documentation written by experts being a bit confusing for newbies. That's a common problem. My customers often struggled with my team's documentation for the same reason. It's hard to forget everything you know and write for a completely uninformed audience. Because of that, I have no beef with the manual's language regarding the programming interface. I do, however, have problems with demos not working (see my la
  9. OK, I'm a newbie just trying to run a demo provided for my new Arty S7-25 board, specifically the Arty S7 General I/O Demo, and I'm quite frustrated. I think these demos are intended for newbies like myself, and as such, I expect them to run without a hitch. They don't. I installed Vivado per the instructions given on the Installing Vivado, Vitis, and Digilent Board Files page. I then downloaded the zip file identified for my Arty S7-25 board and successfully installed it via the instructions given for Vivado (as opposed to SDK Hardware Handoff) on the Using Digilent Github Demo Projects pa
  10. RodRico

    Simple Newbie Question

    Your excellent response and cleared up my confusion zygot. Thanks! My Arty S7 board does have through hole tabs on the USB connector but I plan to 3D print a base for the board that will support all cables and PMODs just to ensure there's never too much stress applied to board connectors.
  11. I'm using Vivado v2020.2 (64-bit) with a newly purchased Arty S7. The Arty manual shows a schematic with USB (J10) connected to the JTAG interface of the FPGA and says "A PC can use the Digilent USB-JTAG circuitry (port J10) to program the FPGA any time the power is on" then goes on to say "The Xilinx tools typically communicate with FPGAs using the Test Access Port and Boundary-Scan Architecture, commonly referred to as JTAG. During JTAG programming, a .bit file is transferred from the PC to the FPGA using the onboard Digilent USB-JTAG circuitry (port J10) or an external JTAG programmer, such
  12. I already looked at J1. It's very clever and elegant, but too minimalist; I plan to implement a full development system with a MicroSD card file system, communication stacks, editor, debugger, VGA output, PS/2 keyboard, etc. I already own a Digilent Arty S7, VGA PMOD, and PS/2 PMOD which I will use for development. I plan to use BRAM for storage and one DSP48E slice for multiply, add, subtract, AND, OR, and XOR. I should be able to fit into a $18.76 (qty 1) XC7S15 with 18KB - 31.5 KB RAM (40% to 70% BRAM utilization) or a $31.78 (qty 1) XC7CS25 with 31.5KB to 63KB RAM (16% to 31% B
  13. Of course there are errors in the immense library of documentation. They do, however, make things very hard for people like me just starting out. Errors are understandable. So is a bit of user frustration.
  14. Thanks for all the great info Dan! My last hands-on experience was quite some time ago, and I now see that *everything* has changed and the learning curve is steep. I'm used to using hierarchal schematic designs, not verilog or VHDL, and am certainly not prepared for designing AXI based systems yet! Some context... I've got a number of products in development that require an embedded controller, and I *really* don't like the complexity of the typical software development workflow in embedded systems, so I'm looking at building a FORTH core (note I was a FORTH consultant back in the day a
  15. @[email protected], Thanks! I just downloaded the AXI reference guide and don't find it too offensive (yet). At first glance, it appears to just be another generic interfacing standard. Does it impose a lot of overhead in terms of throughout or resource use?