mjrx7

I am trying to simulate the DVI2RGB IP but when I run the simulation and feed in 1010101011 (sending in LSB first) the IP shows that it is receiving 0101011101, pState in phaseAlign stays in idle mode, pBlankBegin remains 0, and pTimeoutOvf remains 0, so therefore it never tries to shift the data around to find the proper sequence of where it begins and ends. I'm not sure if I'm handling the reset incorrectly. I am generating a 200 MHz reference clock using the clocking wizard, and I am using the locked signal out of clock wiz to bring the DVI2RGB IP out of reset (aRst). pRst I have tied to '0', resets set to active high. Thanks, Matt