Jorgep

Hello, I'm using an AD5 on a Zybo Z7 which has double PMOD ports, so I use 6 out of the 12 pins available. When I use the provided IPs, they take over all 12 pins on the port, so the bottom part of the double PMOD remains unavailable to use with another device. 1) Is there any way to limit the pins used to just the 6 needed? 2) If not, is one instance of the IP able to drive two AD5s on the double PMOD port? If it is, which address should I use for the second AD5 (considering first AD5 uses base address)? 3) On the Zybo, is it possible to use JF (MIO exclusive PMOD port) with an AD5? I haven't been able to do so yet. Thanks in advance.

Hi @JColvin, Any news on the status register question?

@JColvin any news on either this or the fix for the IPs on 2020.2?

Hey @JColvin, Don't know if I'm supposed to open a new thread for this, but I've been using the PMOD AD5 with 2018.3 for now, and I want to use all 8 pseudo-differential channels. While I'm able to read them using the .c and .h files, I have to read the status register to know what channel each sample belongs to. To work around this, I tried to modify the DAT_STA bit on the mode register but I can't seem to receive the status register's contents that way with the supplied C code. How should I modify the code to allow this? Thanks!

Thank you very much! Do you have any idea how long this may take?

Hello, I installed Vivado 2020.2 on a new machine, and tried to get the PMOD AD5 working by following these instructions (I had it working before on a 2018.3 machine without issues). Bitstream failed with the following errors: [DRC NSTD-1] Unspecified I/O Standard: 4 out of 138 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: jc_pin9_io, jc_pin8_io, jc_pin7_io, and jc_pin10_io. [DRC UCIO-1] Unconstrained Logical Port: 4 out of 138 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: jc_pin9_io, jc_pin8_io, jc_pin7_io, and jc_pin10_io. How do I fix this? Is it related to the Digilent Vivado library not having a 2020 version? Edit: Forgot to mention I'm using a Zybo Z7-20.