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  1. ach

    Arty7-100 DDR3 MMCM problem

    Thanks. Yes you are correct, I really do not know what I am doing or what I changed. Before your reply on Dec 4 I started from scratch i.e. I took an arty 100 reference design and added stuff to it and it was all fine. Made good progress. Then I screwed around with some custom IP (changed a reset to a ~reset) on a test pattern generator. That got things all messed up. Then regenerating messed up the mig with the above error again (after 3 weeks). Now, I have sys_clock into the mig 166.667 MHz, ref_clk 200 MHz and in the mig clock period 3.225ps freq = 310.08 MHz. Now in the freq screen th
  2. I have an UART & a DDR3 controller on an Arty 7 -100 board. The UART talks to minicom. Hello world worked, then I dont know what I changed but now I get the error below. . I then started a completely new project and that one works fine without the error. So I went back to the previous project and tried reset_synth and it still fails. Both the IDE diagrams look the same, use the same xdc file. What do I need to do to fix this error. [DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 333.333 MHz (CLKIN1_PERIOD, net pll_clk3) for the VCO opera
  3. Hi, This is using vivado 2019.2 I have reset going into active low sync_reset of the MIG generating a DDR3 for the arty 100 board. sys_reset which is active low is connected to the board reset pin C2 which is normally high but goes low when pressed. ui_clk_sync_rst is only connected to ex_reset_in of the Processor System Reset whose output mb_reset goes to the microblaze. I also have a UART connected to a serial port on a linux terminal (using minicom). Program is not doing memory for now, just a hello world to the uart via a print. When I first build it and run it I see "hello
  4. Hi Could someone point me to a reference design which uses a microblaze, ddr3, flash on the ARTY 7-100 board. I see such designs for the ARTY 7-35 board in Vivado 2015.1 but I have the 100 board. I took the gpio design (which has a microblaze, flash, ddr) for the arty7-35 board and I get a bit file. I then went and changed the board to arty7-100 and I get errors on the qspi_flash_sck [DRC UCIO-1] Unconstrained Logical Port: 1 out of 23 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board powe