Kyle_ISL
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Kyle_ISL reacted to an answer to a question:
Removing debug logic of pcam-5c reference design
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Hi, there! I'm trying to utilize the pcam to test my convolution module. My plan is adding ip block between AXI4-Stream to Video Out where Video(RGB) data is come from memory(DRAM) and RGB to DVI Video encoder, just like a picture below. To do so, I need to know the information of video data(RGB). My questions are, -What is the resolution of the video is? -What is the frequency of pixclk? -How many clock should be counted to stream out 1 row, and how many rows are there for 1 frame? -How long vsync and hsync becomes 'HIGH' to distinguish each column and row? -How many VDE signal(at rgb2dvi encoder) is work along sync signal. Since there are too many modules in VHDL and so many application, I cannot write the test bench to find out the information that i'm looking for. Could you answer my question, or let me know the way to find out? Thank you, Have a good day!
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Kyle_ISL reacted to an answer to a question:
Removing debug logic of pcam-5c reference design
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You solution make my board work!! I really appreciate you for your help!!
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Hello, I'm using zybo z7-20, Pcam 5c with vivado 2019.1 for Zybo Z7 -20 Pcam 5C Demo 2019.1 release. I followed all the steps in https://github.com/Digilent/Zybo-Z7-20-pcam-5c?_ga=2.30634943.1211223159.1605501220-381318644.1601993729. The program runs with no error, but I can't get the any image on the screen or the menu on the terminal. The video shows my monitor while I'm following demo instruction step. Plz let me the reason why it is not working.
