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  1. There was timing failure when ILA is used. The issue got solved . There are no timing failures now.
  2. Hello, I am trying to implement the similar design. But I coudnt Debug the ADC_DATA. I get the timing failure. Do I need to modify the constraint file? I am using the eclypse-z7/low_level_zmod_adc_dac demo project as reference. Thank you.
  3. naks

    Regarding Eclypse Z7

    Hello, This is my first fpga design. I am new to digital design. I am using Eclypse Z7 board with Zmod ADC. My question might be illogical, but I wanted to clarify my thought. Data coming from Zmod ADC is send to BRAM. I wanted to monitor data coming from ADC and also data coming out from ZmodADC controller IP. I have used ILA debug , but I couldnt monitor the ADC data. In set up Debug there was no clock domain selected for these data. I tried to give clocks available but there is timing failure in Implementation. Is there a way that I could observe my inputs and outputs f