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  1. Hi, @JColvin, Thank you for your response - that explains the difference in the constraints. I went back a re-checked, and you are correct; it only generates a warning, not an error. For example, if I create a 4-bit input named "bus_in" and connected it to switches 12-15 I get the following warning: However, since input bus is just connected to switches switches and not to an actual bus, this difference in I/O standards should not be a problem. Thanks, JNestor
  2. He The master constraint file for the Nexys A7 sets voltage levels for all pins to LVCMOS33 *except* pins T8, and U8, which are connected to switches SW[8] and SW[9], respectively. These two pins are set to LVCMOS18 instead. Is there any reason why these to pins are not set to LVCMOS33 voltage levels? When using the switches to input a multiple-bit input this causes an error when synthesizing in Vivado. Thanks!