Larry

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  1. That was the original design of not disconnecting the 12MHz clock. I thought that was used for the USB and other peripheral circuits. Without a complete set of schematics it is hard to know what is connected to what. The master constraint file is always a good starting point. Using a separate file for complex designs is a good idea. Thank-you for your suggestions and pointing out possible problems with variations of the design.
  2. Thanks for your quick response. I believe you answered all my questions. I was more concerned about adding the second clock to another pin. From your response it sounds like I should disconnect the original 12 MHz clock, from the FPGA, as it would simplify the system. Unfortunately the Cmod S7 schematics do not show the crystal frequency source ( I believe it is IC5 ) or how else it is used on the board. From the information that is provided removing R75 should disconnect the 12 MHz clock from the FPGA. Thank-you for you help. The next step would be to try it and see what problems d
  3. I have checked this forum and other locations and not found any information concerning this problem on a Cmod S7. To maintain synchronization in my system I would like to substitute the on board 12MHz with a 25 MHz clock. The on board clock is feed to the FPGA though pin M9 (an MRCC input on bank 14). I was planning to feed the new 25 MHz clock through Pmod pin J7 (also a MRCC input on bank 34). I was not planning to disconnect after connecting the new clock. After connecting the new clock I believe that I must make some changes to the Constraint File so the board recognizes and uses the