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  1. Thank you for your comments. I'll check web pages you linked! Personally, I was guessing the procedure. -Using any D.L. framework, create a weight file that matches the real configuration (FPGA channel or I/O) -Rewrite it to C++ and put it on FPGA with Micro-blaze (soft CPU) -Based on FPGA input: High/Low, FPGA provides High/Low following the weight file. But, if #of FPGA I/O is not sufficient, a couple/few of FPGA must be used. In that case, how is communication among them done.... Anyway, I have to investigate it. PYNQ is probably helpful to brus
  2. Are there any introductive hands-on web pages or articles on Deep/Machine learning on FPGA Artix7 (not ZYNQ or PYNQ) ?? I'm doing deep learning using Tnsorflow or KELAS, and now, I'm thinking of performing it on FPGA Artix7. But, I do not have any clues to start it. If someone knows useful information, could you tell me. Best regards.
  3. Tim.O

    50 MHz clock

    > looks like you're using some clocking features (DCM_CLKGEN) from Spartan-6 devices that no longer work or are unreliable with 7-series devices I see. I did not know it... (;_;) Thank you very much for your comments. I will check it ”Templates within Vivado”
  4. Dear zygot thank you for the comment. > I get the feeling that you are ... Yes, because I have never touched UART communication on FPGA program and there is an example of Hello World in the tutorial, I started to use MicroBlaze to communicate with PC via UART. After I posted a question on it here, I got several comments and found that direct UART communication without Microblaze is possible, and now, I can do it on my FPGA with commands (python script) from terminal. Thanks!
  5. Tim.O

    50 MHz clock

    I'm trying to generate 25 MHz clock from 100 MHz (Basys3, Vivado19) in a code below. But, it seems it is 50 MHz Multiplying 100 by 8 and divide it by 2, and divide it again by 16, then I though CLKFXDV is 25MHz. What is wrong? DCM_CLKGEN_INST1 : DCM_CLKGEN generic map ( CLKFX_MULTIPLY => 8, -- Multiply value - M - (2-256) CLKFX_DIVIDE => 2, -- Divide value - D - (1-256) CLKFXDV_DIVIDE => 16, -- CLKFXDV divide value (2, 4, 8, 16, 32) CLKFX_MD_MAX => 4.0, -- Specify maximum M/D r
  6. Dear zygot > MicroBlaze or NIOS might be required if you are constrained to doing design Yes, for the time being, I do not need C libraries, So I removed Microblaze from my design. But, at some point, I would like to use C or python on FPGA, then, I will again start to use soft-processors. And that you for the nice summary showing possible measures to communicate with FPGA
  7. Dear [email protected] Thank you for your comment. >Microblaze is not required for serial communication. I have many projects that .... After I got this message, I started to look for how people are controlling uart without Microblaze, and I found several VHDL examples. And now, I'm controlling it without Microblaze.
  8. Do anyone knows whether MicroBlase is necessary for serial communication between FPGA (in Basys3, for instance) and PC, especially for sending and receiving data? or MicroBlase is not necessary for it? Best regards.
  9. Thank you for your comments, and sorry for my unclear question due to lack of my knowledge on FPGA development. > .... control the FPGA while it is already powered on Yes, this is close to what I want to do. I give a command (like ./TakeData) via serial communication and FPGA starts count something (for instance, clock) and send it to me. This is what I want to do as the first step. > If you are wanting to control the board.... Yes, this is one way. But, for the moment, I have basys3 only, and try to investigate what I can do with this. I found that MicroBlaze +
  10. I put the same question Xilinx forum, but, nobody knows it... If someone know it, please tell me... I'm testing Hello World using MicroBlaze on Artix7 (Basys3) by referring to, for instance, https://reference.digilentinc.com/learn/programmable-logic/tutorials/basys-3-getting-started-with-microblaze/start It works. I would like to do it from terminal something like ./HelloWorl.exe via serial communication with FPGA. And in the future I want to control FPGA, read data from buffer, etc. It means Command Line Session. Are there any useful example or useful web pages to unde