Thank you for your comments. I'll check web pages you linked!
Personally, I was guessing the procedure.
-Using any D.L. framework, create a weight file that matches the real configuration (FPGA channel or I/O)
-Rewrite it to C++ and put it on FPGA with Micro-blaze (soft CPU)
-Based on FPGA input: High/Low, FPGA provides High/Low following the weight file.
But, if #of FPGA I/O is not sufficient, a couple/few of FPGA must be used. In that case, how is communication among them done....
Anyway, I have to investigate it. PYNQ is probably helpful to brush my knowledge up...