tt12345678

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  1. Many apologies: in fact, the system works perfectly, I just didn't read the instructions properly (you have to press a button to operate the LMS noise canceller). I'm still puzzled as to what the timing warnings mean.
  2. I have just come across the same problem as @greedyhao and was wondering if anyone else has. The tutorial involves using IP generated from the Matlab HDL coder in a previous tutorial, but they also provide the packaged IP for those, like me, who don't have access to Matlab. I'm using Vivado/Vitis 2020.1 and the tutorial uses software from 2015 so it took a bit of effort to get things to work at, e.g. port names were different from those in the provided constraints file and the IP Makefiles didn't work, but everything built in the end. In fact, the whole thing runs on the Zedboard but the
  3. Hi @Bianca I bought it last month and it's a revision D.
  4. Hi @JColvin Thanks very much for your answer, it's very helpful. In the meantime, I've been going through some of the Zynq Book tutorials. They seem pretty good, although it's a bit of a challenge getting some of them to work in Vitis 2020.1, which seems to have some bugs in the IP creation bit. I suppose coming across problems improves understanding in the long run.
  5. Hello My name is Tony. I'm a total beginner but am hoping eventually to be able to use a Zedboard to stream data from an AD7768 evaluation board to a PC.
  6. I have recently bought a Zedboard and as a complete and utter beginner I thought I'd start with the Digilent tutorial, https://reference.digilentinc.com/vivado/getting_started/v2019.2 . I got as far as trying to edit the constraint file Zedboard-Master.xdc as in Section 6.7. The master files are in https://github.com/Digilent/digilent-xdc/archive/master.zip?_ga=2.2696439.638022708.1602322154-505626126.1588185805 At that point I got stuck: the tutorial says the clock port will be at the top of the xdc file and followed by a create_clock line. However, the clock port isn't at the top and th