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  1. when my clock has been switched to a higher frequency, I need to repeat the case loop again. However, I have an issue to reset my count to 0 and repeat the loop again while maintaining the higher clock frequency. So how do I solve this issue? Below are the conditions I used: always @ (posedge myclk) begin clkout <= (out_count == 5)? slowfclk : slowclk; end always @ (posedge clkslt) begin out_count <= (out_count == 5)? 5: out_count + 1; case(out_count): .........