Hello,
I'm using zybo z7 2010, Pcam 5c with vivado 2019.1 for Zybo Z7 -20 Pcam 5C Demo 2019.1 release. I the following steps.
1. open project
2. change device to zybo z7 7010
3. update all IPs
4. create HDL
5. synthesis and impliment.
I'm getting no error till here but following critical warnings after open implementation.
[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
6. generate bit
7. export to hardware (include bitstream)
8. lanch SDK
after this I followed the exact steps given on README file on github.
9. program fpga
10. and run as debug
I'm getting no error but still not able to get the image on the screen or the menu on the terminal.
