LenR

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About LenR

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  1. My goal is to create a music synthesizer, the two ENC are for menu traversal, the OLED is to display the menu and the uart will connect a USB to a MIDI input and output. I need to add the I2S2 and I have an I2C and SIO for various attached devices. I don't know if all will be needed, but I am also seeing what I can cram into an S750. Push it until it cries uncle so to speak. I am also interested in porting Forth as close to the hardware as I can, in which case I may not need the Microblaze, but I think the approach I am taking will get me learning the system, its strengths and weaknesses as fa
  2. Forgot the screen cap of the timing violation on implementation.
  3. Another question, I didn't include the Quad SPI Flash because I assumed that would only be needed in the design if I was going to use it in a program and that the initialization of the FPGA is something the board handles and no additional software is needed. Please tell me if I need to include it for that to work. Thanks.
  4. Just to see what would happen, I went ahead inspite of the "Critical Warnings" and ran the Synthesis and when that completed with no problems, I ran the implementation, then the Generate Bitstream which also appeared to work. I got another warning from Synthesis about timing violations during setup and there were some other warnings earlier which I have included. I will try to find out as much about these warnings as possible and fix them if I can. Some it may turn out I can ignore, but the each of these look like they could be a problem. When I generated the system after creating the Mig
  5. I would say there is sufficient difference between the S7 and the pmod doc that it could use it's own doc. I started a new project and used your modifications one interesting thing that happened was the board sources display quit showing the ddr_clock input as used, but the block diagram shows it and validates ok. I did get those critical warnings about the board revision and the critical warning about the mig_7series_0 device temp not used. I know if I make it external that one will go away, but am stumped about the rest.
  6. I'm using 2020.1 and I followed the guide, Neither of the links to the files at the beginning of the reference work, but I just went to the gethub site and picked them up there. I think it will solve most of the problems but it created a new one. There was a bunch of critical warnings that basically requires a board descriptor revision of 1.1 and both my S725 and s750 are at a level of 1.0. I have tried updating the revision, but it is stuck at 1.0. After closing the project and starting another just to see if that would let the board descriptor update, I came back to the project and even
  7. When I create a block diagram for the Arty S750 I add a MicroBlaze then after running the wiz I add each of the items listed under Board. When I get to the PMods it says it can't do it because there is no possible options to connect. How do I add the PMods?
  8. This morning I started a new project, created a MicroBlaze ran the automation wiz and added the items that were listed under board each followed by running the wiz when it was available. I got the same error about not being able to put reset_0 where reset was so I looked at the block diagram and sure enough both were there as inputs. I deleted reset and connecting the destinations from that to reset_0. Problem solver. I have another about putting the Pmods into the diagram, but I will start another question for that.
  9. I got three critical warnings about setting pins. port reset_0 can not be placed ... because it is occupied by port reset port sys_ clock can not be placed ... because it is occupied by port sys_clock_1 port reset_0 can not be placed ... because it is occupied by port reset Yes, the first and last are duplicates, but it is telling me I can override the board assignments, but it was all generated by Vivado. I placed a Micro Blaze in the design then went to the board dropdown and added almost all the stuff on the board, running the helper after each. Validation was good