Sridhar

Hello All, I am Sridhar, getting into FPGAs and ASIC designs and Verilog since Feb 2020. Having some experiences in electronic hardware development, and now trying to add vlsi into my career. Now been able to write RTL code, develop test bench in System Verilog, simulate in Vivado, can synthesize, implement and generate bit stream files. Able to understand couple of errors and critical warnings, can solve them. Now talking to my basys-3. See you around the forum topics. Have a good day!