3rdClassLidlToaster

Hi, I just read the documentation of Xilinx XFFT IP V9.1, read some of the forums threads and also did some testing, but still had some questions especially as far as the IFFT Mode of the IP is concerned. Perhaps somebody did similar experience and can refer to some of them. 1) Is it correct that IFFT mode of IP adds an intrinsic scaling of 1/N to its input which can't be prevented and which is independent from the configuration of the IP and the eventually configured scaling schedule on axi_stream_config bus ? With relation to previous question, is it correct that if i do a scaled FFT (scaling schedule or auto scaling) and put the result vector into IFFT i can't get back original amplitude of time signal because [scaled FFT + intrinsic scaled IFFT] resulting in kinda double scaling ? So with relation to previous question, if approach would be to get back to original time signal after FFT + IFFT an unscaled FFT had to be chosen ? 2) If i choosed the option "natural order" for FFT output and then put the output vector back into IFFT again (after switching from FFT mode to IFFT mode on axi_stream_config bus), do i have to reorder the indices of the vector first to get original time signal back, or can i leave the order as it is (if configuration of IP remains unchanged except switching it to IFFT) ? 3) Is it normal that IFFT doubles the frequency of original signal in its output vector (so that if original FFT input was 1 Period of time signel, you will receive 2 Periods in IFFT output) or is this a mistake in my test application ? 4) Does the "scaling schedule" on the axi_stream_config bus (if the IP is configured for manual scaling) have to be sent only once before starting to read in a frame, or does it have to be sent repeatedly for each sample during the data read in process? 5) Is it necessary to reset the core via the optional "aresetn" port before or after sending a new configuration via the axi_stream_config bus ? Ty and Greetings

Hi, I had two questions concerning Signal generation with Zynq SoC or FPGA. As far as i know there would be four methods to realize a signal generator: Using DDS compiler IP; Using CORDIC IP; Make own implementation in Micorcontroller Part of SoC; Make own implementation in PL Part or FPGA 1) Are these all possibilities for Implementation or i forgot one ? 2) What are the advantages and disadvantages comparing these possibilities ? Greetings

Hi, Yes. It's neither frequency or phase, you have to calculate sqrt(real^2 + imag^2) to get the amplitude and arctan(imag/real) to get the phase. This can be done manually or with ip cores like CORDIC core. If you want the exact values of amplitudes in original signal you have to divide the calculated amplitude by your FFT resolution and multiply it by 2 additionally. Also its important that you choose your FFT resolution accordingly so that you know on which position in the array of complex FFT values you can find the frequency of your interest. That makes no sense. The output on m_axis_data_tdata of FFT is the input signal in frequency domain. The input of s_axis_phase_tdate is the phase increment for the accumulator of your DDS and refers to the the output frequency of your DDS in the time domain. You have to calculate a value for phase increment according to the desired output frequency of your cosine and then put this value into s_axis_phase_tdata port of your DDS. Greetings

Hi i have a question, Is it possible to switch ZMOD DAC 1411 from DC to AC Coupling ? The documentation of LLC IP contains a description of a Port/Input which is called "kCh1CouplinStatic" and "kCh2CouplinStatic" but these are not present in the IP configuration options neither in external nor in internal configuration mode. The Zmod ADC offers these feature but the DAC seems not despite the parameter exists in the documentation. Greetings

Hi i had short question concerned Eclypse Z7 Zmod ADC and DAC and thier Controller IPs and according librarys. Are the functions of the axi zmod library essentially to write to config registers of axi_zmod_ips or can they be written directly with simple functions like xil_out32(baseAddress + registerAddress, value) or a simple pointer to baseAddress of IP on axi bus ? The reason i ask this is, that i build a very basic project with only the ZMOD_DAC_AXI_IP connected to PS with AXI-Lite config port and the ZMOD_DAC_Low_Level_Controller_IP connected to ZMOD_DAC_AXI_IP (without DMA and all this stuff) and only try to write to the control_reg (0x00) with this very simple code: uint32_t *dac_axi_ctrl; int main() { first approach: uint32_t *dac_axi_ctrl; dac_axi_ctrl = (uint32_t *)0x43C10000; // baseAddress of ZMOD_DAC_AXI_IP from xparameters file. *(dac_axi_ctrl + 0) = 0x00000010; other approach i tried: xil_out32(0x43C10000, 0x00000010); uint32_t value = xil_in32(0x43C10000); xilprintf("%i", value); } Only thing i try here is to switch on ADC output and hear to the clicking of the relay but nothing happens. I know that this task is also doable on Input Pins of Low level controller directly but i also have to do things like switch the output format of DAC from "offset binary" to "twos complement" and things like this are only doable over SPI with Axi_IP controller. But i want to do this without this bloated librarys encapsulating standard functions like xil_out32() in a bunch of upper level functions and i also won't use DMA, Flash and circular buffer and all these stuff from the examples. Or to sum up all this: Are the ips kinda "locked" on the library functions or is it not a normal axi lite bus and the library with all stuff like building constructor of ZMOD class and other stuff from the example has to be used to write to config registers ? So it can't be threaten as a custom AXI Ip in the kind of writing to it via AXI with basic functions ? Greetings Rabobsel